[PATCH linux dev-4.7 6/8] mtd: spi-nor: aspeed: prepare for fast read

[Cédric Le Goater]

On 11/07/2016 03:29 AM, Joel Stanley wrote:
> On Sat, Nov 5, 2016 at 3:30 AM, Cédric Le Goater <clg at kaod.org> wrote:
>> Include dummy cycle in the control register value which will be
>> required for fast read.
>>
>> Signed-off-by: Cédric Le Goater <clg at kaod.org>
>> ---
>>  drivers/mtd/spi-nor/aspeed-smc.c | 41 +++++++++++++++++++++++++++++++++++-----
>>  1 file changed, 36 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c
>> index 73adf409ac34..444af3aff8b5 100644
>> --- a/drivers/mtd/spi-nor/aspeed-smc.c
>> +++ b/drivers/mtd/spi-nor/aspeed-smc.c
> 
>> @@ -304,6 +304,10 @@ struct aspeed_smc_controller {
>>                                        CONTROL_SPI_IO_DUMMY_CYCLES_LO_SHIFT)
>>  #define CONTROL_SPI_IO_DUMMY_CYCLES_MASK (CONTROL_SPI_IO_DUMMY_CYCLES_HI | \
>>                                           CONTROL_SPI_IO_DUMMY_CYCLES_LO)
>> +#define CONTROL_SPI_IO_DUMMY_CYCLES_SET(dummy)                         \
>> +       (((((dummy) >> 2) & 0x1) << CONTROL_SPI_IO_DUMMY_CYCLES_HI_SHIFT) | \
>> +       (((dummy) & 0x3) << CONTROL_SPI_IO_DUMMY_CYCLES_LO_SHIFT))
>> +
> 
> This is a bit hairy.

yeah. The SoC does a lot of bit recycling : 1 bit there, 2 bits 
there. it is error prone for drivers ...

Thanks,

C. 

> 
> Aside from that,
> 
> Reviewed-by: Joel Stanley <joel at jms.id.au>
> 
> Cheers,
> 
> Joel
>