[linux dev-4.7 PATCH 3/4] arm: aspeed: Remove setting of SCU90 from common

[Andrew Jeffery]

On Fri, 2016-11-04 at 09:00 +1030, Joel Stanley wrote:
> This hack enabled I2C buses 3 to 8 inclusive:
> 
>    Enable I2C8 function pins: 0x1
>    Enable I2C7 function pins: 0x1
>    Enable I2C6 function pins: 0x1
>    Enable I2C5 function pins: 0x1
>    Enable I2C4 function pins: 0x1
>    Enable I2C3 function pins: 0x1
> 
> Bit 3 set the USB1.1 Host port 2 function, which is not yet supported in our
> kernel.
> 
> Bits 13 and 15 disabled the RGMII/RMII 1 and 2 RX pin internal pull down which
> is the default state.
> 
> Therefore all functionality is present in the device tree and this can be
> removed.
> 
> Signed-off-by: Joel Stanley <joel at jms.id.au>

Reviewed-by: Andrew Jeffery <andrew at aj.id.au>

> ---
>  arch/arm/mach-aspeed/aspeed.c | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c
> index cfbd6d3b3b73..46e711ca275c 100644
> --- a/arch/arm/mach-aspeed/aspeed.c
> +++ b/arch/arm/mach-aspeed/aspeed.c
> @@ -58,7 +58,6 @@ static void __init do_common_setup(void)
>  	/* TODO: This should go in the GPIO driver device tree bindings */
>  	writel(0x01C000FF, AST_IO(AST_BASE_SCU | 0x88));
>  	writel(0xC1C000FF, AST_IO(AST_BASE_SCU | 0x8c));
> -	writel(0x003FA008, AST_IO(AST_BASE_SCU | 0x90));
>  
>  	/* Setup scratch registers */
>  	writel(0x00000042, AST_IO(AST_BASE_LPC | 0x170));
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