[linux dev-4.7 PATCH 2/4] arm: aspeed: Remove Palmetto SCU hack
Andrew Jeffery
andrew at aj.id.au
Fri Nov 4 14:05:37 AEDT 2016
On Fri, 2016-11-04 at 09:00 +1030, Joel Stanley wrote:
> The Palmetto would write the following state into the SCU, which is now covered
> by pinmux:
>
> Enable MAC#1 MDIO1: 0x0
> Enable MAC#1 MDC1: 0x0
> Enable NOR flash ROMA25: 0x0
> Enable NOR flash ROMA24: 0x0
> Enable flash ROMCS4#: 0x0
> Enable flash ROMCS3#: 0x0
> Enable flash ROMCS2#: 0x0
> Enable flash ROMCS1#: 0x1
> Enable NOR flash ACK control input pin: 0x1
> Enable BMC IRQ# interrupt output: 0x1
> Enable BMC IRQ# interrupt output polarity: 0x0
> Enable Reserved: 0x0
> Enable VPIR9: 0x0
> Enable VPIR8: 0x0
> Enable VPIR7: 0x0
> Enable VPIR6: 0x0
> Enable VPIR5: 0x0
> Enable VPIR4: 0x0
> Enable VPIR3: 0x0
> Enable VPIR2: 0x0
> Enable VPIR1: 0x0
> Enable VPIR0: 0x0
> Enable VPIG9: 0x0
> Enable VPIG8: 0x0
> Enable PWM7 or VPIG7: 0x0
> Enable PWM6 or VPIG6: 0x1
> Enable PWM5 or VPIG: 0x1
> Enable PWM4 or VPIG: 0x1
> Enable PWM3 or VPIG: 0x1
> Enable PWM2 or VPIG: 0x1
> Enable PWM1 or VPIG1: 0x1
> Enable PWM0 or VPIG0: 0x1
>
> Signed-off-by: Joel Stanley <joel at jms.id.au>
Reviewed-by: Andrew Jeffery <andrew at aj.id.au>
> ---
> arch/arm/mach-aspeed/aspeed.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c
> index 202bf3d9d467..cfbd6d3b3b73 100644
> --- a/arch/arm/mach-aspeed/aspeed.c
> +++ b/arch/arm/mach-aspeed/aspeed.c
> @@ -115,9 +115,6 @@ static void __init do_palmetto_setup(void)
> /* Setup PNOR address mapping for 32M flash */
> writel(0x30000E00, AST_IO(AST_BASE_LPC | 0x88));
> writel(0xFE0001FF, AST_IO(AST_BASE_LPC | 0x8C));
> -
> - /* SCU setup */
> - writel(0x01C0007F, AST_IO(AST_BASE_SCU | 0x88));
> }
>
> static void __init do_firestone_setup(void)
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