[PATCH qemu 2/2] ast2400: Integrate the SCU model and configure reset values

[Joel Stanley]

On Thu, Jun 9, 2016 at 3:14 AM, Andrew Jeffery <andrew at aj.id.au> wrote:
> Almost all configured reset values are specified by the datasheet. The
> exception is ASPEED_SCU_SOC_SCRATCH1, where we mark the DRAM as
> successfully initialised by the SoC to avoid unnecessary dark corners in
> the SoC's u-boot support.
>
> Signed-off-by: Andrew Jeffery <andrew at aj.id.au>
> ---
>  hw/arm/ast2400.c         | 47 +++++++++++++++++++++++++++++++++++++++++++++++
>  include/hw/arm/ast2400.h |  2 ++
>  2 files changed, 49 insertions(+)
>
> diff --git a/hw/arm/ast2400.c b/hw/arm/ast2400.c
> index 4a9de0e10cbc..240da180befa 100644
> --- a/hw/arm/ast2400.c
> +++ b/hw/arm/ast2400.c
> @@ -24,12 +24,46 @@
>  #define AST2400_IOMEM_SIZE       0x00200000
>  #define AST2400_IOMEM_BASE       0x1E600000
>  #define AST2400_VIC_BASE         0x1E6C0000
> +#define AST2400_SCU_BASE         0x1E6E2000
>  #define AST2400_TIMER_BASE       0x1E782000
>  #define AST2400_I2C_BASE         0x1E78A000
>
>  static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
>  static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
>
> +static const AspeedSCUResetCfg scu_reset[] = {
> +    /* Values are defaults from the datasheet except where noted */
> +    { ASPEED_SCU_SYS_RST_CTRL,   0xFFCFFEDCU },
> +    { ASPEED_SCU_CLK_SEL,        0xF3F40000U },
> +    { ASPEED_SCU_CLK_STOP_CTRL,  0x19FC3E8BU },
> +    { ASPEED_SCU_D2PLL_PARAM,    0x00026108U },
> +    { ASPEED_SCU_MPLL_PARAM,     0x00030291U },
> +    { ASPEED_SCU_HPLL_PARAM,     0x00000291U },
> +    { ASPEED_SCU_MISC_CTRL1,     0x00000010U },
> +    { ASPEED_SCU_PCI_CTRL1,      0x20001A03U },
> +    { ASPEED_SCU_PCI_CTRL2,      0x20001A03U },
> +    { ASPEED_SCU_PCI_CTRL3,      0x04000030U },
> +    { ASPEED_SCU_SYS_RST_STATUS, 0x00000001U },
> +    { ASPEED_SCU_SOC_SCRATCH1,   0x000000C0U }, /* SoC completed DRAM init */
> +    { ASPEED_SCU_MISC_CTRL2,     0x00000023U },
> +    { ASPEED_SCU_RNG_CTRL,       0x0000000EU },
> +    { ASPEED_SCU_REV_ID,         0x02000303U },
> +    { ASPEED_SCU_PINMUX_CTRL2,   0x0000F000U },
> +    { ASPEED_SCU_PINMUX_CTRL3,   0x01000000U },
> +    { ASPEED_SCU_PINMUX_CTRL4,   0x000000FFU },
> +    { ASPEED_SCU_PINMUX_CTRL5,   0x0000A000U },
> +    { ASPEED_SCU_WDT_RST_CTRL,   0x003FFFF3U },
> +    { ASPEED_SCU_PINMUX_CTRL8,   0xFFFF0000U },
> +    { ASPEED_SCU_FREE_CNTR4,     0x000000FFU },
> +    { ASPEED_SCU_FREE_CNTR4_EXT, 0x000000FFU },
> +    { ASPEED_SCU_CPU2_BASE_SEG1, 0x80000000U },
> +    { ASPEED_SCU_CPU2_BASE_SEG4, 0x1E600000U },
> +    { ASPEED_SCU_CPU2_BASE_SEG5, 0xC0000000U },
> +    { ASPEED_SCU_UART_HPLL_CLK,  0x00001903U },
> +    { ASPEED_SCU_PCIE_CTRL,      0x0000007BU },
> +    { ASPEED_SCU_BMC_DEV_ID,     0x00002402U }

I can't see the strapping register in here. We use that to configure
the clock driver I'm writing, so it would be handy to have.

Cheers,

Joel