[PATCH linux] arm: aspeed: zaius: Setup LPC to AHB bridge

[Xo Wang]

On Wed, Nov 30, 2016 at 9:49 PM, Xo Wang <xow at google.com> wrote:
>
> Add explicit SPI1 flash windows rather than use boot values.
> Add 64 MiB mapping for LPC host interface to SPI1 CE0's window.
> Add missing call to do_common_setup() which includes enabling LPC FWH
> access cycles.
>
> Signed-off-by: Xo Wang <xow at google.com>
> ---
>  arch/arm/mach-aspeed/aspeed.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
>
> diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c
> index a491cd2..807ccc2 100644
> --- a/arch/arm/mach-aspeed/aspeed.c
> +++ b/arch/arm/mach-aspeed/aspeed.c
> @@ -137,6 +137,8 @@ static void __init do_zaius_setup(void)
>         unsigned long reg;
>         unsigned long board_rev;
>
> +       do_common_setup();
> +
>         /* Read BOARD_REV[4:0] fuses from GPIOM[7:3] */
>         reg = readl(AST_IO(AST_BASE_GPIO | 0x78));
>         board_rev = (reg >> 3) & 0x1F;
> @@ -162,6 +164,24 @@ static void __init do_zaius_setup(void)
>                 reg = readl(AST_IO(AST_BASE_GPIO | 0x00));
>                 writel(reg | phy_reset_mask, AST_IO(AST_BASE_GPIO | 0x00));
>         }
> +
> +       /* Setup PNOR address mapping for 64M flash
> +        *
> +        *   ADRBASE: 0x3000 (0x30000000)
> +        *   HWMBASE: 0x0C00 (0x0C000000)
> +        *  ADDRMASK: 0xFC00 (0xFC000000)
> +        *   HWNCARE: 0x03FF (0x03FF0000)
> +        *
> +        * Mapping appears at 0x60300fc000000 on the host
> +        */
> +       writel(0x30000C00, AST_IO(AST_BASE_LPC | 0x88));
> +       writel(0xFC0003FF, AST_IO(AST_BASE_LPC | 0x8C));
> +
> +       /* Set SPI1 CE1 decoding window to 0x34000000 */
> +       writel(0x70680000, AST_IO(AST_BASE_SPI | 0x34));
> +
> +       /* Set SPI1 CE0 decoding window to 0x30000000 */
> +       writel(0x68600000, AST_IO(AST_BASE_SPI | 0x30));
>  }
>
>  static void __init do_witherspoon_setup(void)
> --
> 2.8.0.rc3.226.g39d4020
>

ping