[PATCH 2/2] gpio: aspeed: Support banks Y, Z, AA and BB
Joel Stanley
joel at jms.id.au
Mon Dec 12 15:06:39 AEDT 2016
These banks have extra limitations compared to those currently
implemented. We must detect when these unique banks are being used and
special case their IRQ and input state.
TODO: Do what it says on the label
Signed-off-by: Joel Stanley <joel at jms.id.au>
---
drivers/gpio/gpio-aspeed.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c
index d7198536de13..c4d87a2a489f 100644
--- a/drivers/gpio/gpio-aspeed.c
+++ b/drivers/gpio/gpio-aspeed.c
@@ -65,10 +65,14 @@ static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
.names = { "U", "V", "W", "X" },
},
/*
- * A bank exists for { 'Y', 'Z', "AA", "AB" }, but is not implemented.
* Only half of GPIOs Y support interrupt configuration, and none of Z,
* AA or AB do as they are output only.
*/
+ {
+ .val_regs = 0x01E0,
+ .irq_regs = 0x0178,
+ .names = { "Y", "Z", "AA", "AB" },
+ },
};
#define GPIO_BANK(x) ((x) >> 5)
@@ -129,6 +133,9 @@ static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, int val
addr = bank_val_reg(gpio, bank, GPIO_DATA);
+ /* TODO: detect when we're dealing with GPIOs that cannot be set as
+ * inputs */
+
reg = ioread32(addr);
if (val)
reg |= GPIO_BIT(offset);
@@ -158,6 +165,9 @@ static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
unsigned long flags;
u32 reg;
+ /* TODO: detect when we're dealing with GPIOs that cannot be set as
+ * inputs */
+
spin_lock_irqsave(&gpio->lock, flags);
reg = ioread32(bank_val_reg(gpio, bank, GPIO_DIR));
@@ -233,6 +243,9 @@ static void __aspeed_gpio_irq_set_mask(struct irq_data *d, bool set)
void __iomem *addr;
int rc;
+ /* TODO: Detect when a bank cannot be used as an IRQ source and return
+ * error */
+
rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit);
if (rc)
return;
--
2.11.0
More information about the openbmc
mailing list