[linux] arm/aspeed: Reset AHB on boot
andrew at aj.id.au
Tue Aug 9 10:01:10 AEST 2016
On Mon, 2016-08-08 at 14:59 +0930, Joel Stanley wrote:
> The Aspeed u-boot port from the Aspeed SDK performed I2C initialisation.
> Part of this appears to require a AHB reset in order to successfully
> access the I2C registers.
> So we can boot the stable kernels on systems with new u-boot we add this
> to the stable kernel tree.
This feels like it's missing a sentence. Something to the effect that
the new u-boot differs in behaviour to the SDK and doesn't do this
Might be worth mentioning that we don't assume any SCU lock state to be
configured by u-boot. Also, that we leave the SCU unlocked here so that
drivers accessing the SCU don't need to manage it themselves. Given we
describe a syscon device in the dt we should be able to coordinate
unlock/lock in individual drivers, but we aren't for the moment.
However, on-the-whole, the patch seems reasonable to me.
Acked-by: Andrew Jeffery <andrew at aj.id.au>
> Signed-off-by: Joel Stanley <joel at jms.id.au>
> arch/arm/mach-aspeed/aspeed.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
> diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c
> index fadbbb666e1d..1102b896cab0 100755
> --- a/arch/arm/mach-aspeed/aspeed.c
> +++ b/arch/arm/mach-aspeed/aspeed.c
> @@ -200,9 +200,14 @@ static void __init aspeed_init_early(void)
> u32 reg;
> + /* Unlock SCU */
> + writel(SCU_PASSWORD, AST_IO(AST_BASE_SCU));
> + /* Reset AHB bridges */
> + writel(0x02, AST_IO(AST_BASE_SCU | 0x04));
> // XXX UART stuff to fix to pinmux & co
> writel(0x02010023, AST_IO(AST_BASE_LPC | 0x9c));
> - writel(SCU_PASSWORD, AST_IO(AST_BASE_SCU)); // UNLOCK SCU
> writel(0xcb000000, AST_IO(AST_BASE_SCU | 0x80));
> writel(0x00fff0c0, AST_IO(AST_BASE_SCU | 0x84));
> writel(0x10CC5E80, AST_IO(AST_BASE_SCU | 0x0c));
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