[PATCH dev-4.7 1/2] net/faraday: Avoid PHYSTS_CHG interrupt

Joel Stanley joel at jms.id.au
Mon Aug 8 18:27:01 AEST 2016

On Tue, Aug 2, 2016 at 2:15 PM, Gavin Shan <gwshan at linux.vnet.ibm.com> wrote:
> On Mon, Aug 01, 2016 at 05:57:02PM +0930, Joel Stanley wrote:
>>On Thu, 2016-07-28 at 11:04 +1000, Gavin Shan wrote:
>>> Bit#11 in MACCR (0x50) designates the signal level for PHY link
>>> status change. It's cleared, meaning high level enabled, by default.
>>> However, we can see continuous interrupt (bit#6) in ISR (0x0) for it
>>> and it's obviously a false alarm. The side effect is CPU cycles
>>> wasted
>>> to process the false alarm.
>>> This sets bit#11 in MACCR (0x50) to avoid the bogus interrupt.
>>I assume you're seeing this with the hardware in NCSI mode?
>>Is the patch okay for other use cases?
> Yeah, the only available testing environment is NCSI. I didn't
> test it on PHY based AST2500. Joel, please give it a shoot on
> your AST2500 board before merging it. By the way, the interrupt
> (PHYSTS_CHG) shouldn't be used even we have a PHY connected as
> polling mechanism is specified to retrieve the link status in
> ftgmac100.c

I gave this a spin on the ast2500 evb. I did get these two messages
when bringing the interface up:

ftgmac100 1e660000.ethernet eth0: [ISR] = 0x200: PHYSTS_CHG
ftgmac100 1e660000.ethernet eth0: [ISR] = 0x200: PHYSTS_CHG

But from then on the device worked as expected, with no flooding of
the kernel buffer.

I have applied the patches to my tree. Thanks!



More information about the openbmc mailing list