[PATCH dev-4.7 1/2] net/faraday: Avoid PHYSTS_CHG interrupt

[Joel Stanley]

On Thu, 2016-07-28 at 11:04 +1000, Gavin Shan wrote:
> Bit#11 in MACCR (0x50) designates the signal level for PHY link
> status change. It's cleared, meaning high level enabled, by default.
> However, we can see continuous interrupt (bit#6) in ISR (0x0) for it
> and it's obviously a false alarm. The side effect is CPU cycles
> wasted
> to process the false alarm.
> 
> This sets bit#11 in MACCR (0x50) to avoid the bogus interrupt.

Thanks.

I assume you're seeing this with the hardware in NCSI mode?

Is the patch okay for other use cases?

Cheers,

Joel

> 
> Signed-off-by: Gavin Shan <gwshan at linux.vnet.ibm.com>
> ---
>  drivers/net/ethernet/faraday/ftgmac100.c | 1 +
>  drivers/net/ethernet/faraday/ftgmac100.h | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/drivers/net/ethernet/faraday/ftgmac100.c
> b/drivers/net/ethernet/faraday/ftgmac100.c
> index e805c4d..f00911a 100644
> --- a/drivers/net/ethernet/faraday/ftgmac100.c
> +++ b/drivers/net/ethernet/faraday/ftgmac100.c
> @@ -224,6 +224,7 @@ static void ftgmac100_init_hw(struct ftgmac100
> *priv)
>  				 FTGMAC100_MACCR_RXMAC_EN	| \
>  				 FTGMAC100_MACCR_FULLDUP	| \
>  				 FTGMAC100_MACCR_CRC_APD	| \
> +				 FTGMAC100_MACCR_PHY_LINK_LEVEL | \
>  				 FTGMAC100_MACCR_RX_RUNT	| \
>  				 FTGMAC100_MACCR_RX_BROADPKT)
>  
> diff --git a/drivers/net/ethernet/faraday/ftgmac100.h
> b/drivers/net/ethernet/faraday/ftgmac100.h
> index c258586..d07b6ea 100644
> --- a/drivers/net/ethernet/faraday/ftgmac100.h
> +++ b/drivers/net/ethernet/faraday/ftgmac100.h
> @@ -152,6 +152,7 @@
>  #define FTGMAC100_MACCR_FULLDUP		(1 << 8)
>  #define FTGMAC100_MACCR_GIGA_MODE	(1 << 9)
>  #define FTGMAC100_MACCR_CRC_APD		(1 << 10)
> +#define FTGMAC100_MACCR_PHY_LINK_LEVEL	(1 << 11)
>  #define FTGMAC100_MACCR_RX_RUNT		(1 << 12)
>  #define FTGMAC100_MACCR_JUMBO_LF	(1 << 13)
>  #define FTGMAC100_MACCR_RX_ALL		(1 << 14)