[PATCH linux 3/3] Initial support for Garrison system.
OpenBMC Patches
openbmc-patches at stwcx.xyz
Wed Apr 27 06:10:58 AEST 2016
From: Brad Bishop <bradleyb at fuzziesquirrel.com>
Garrison is an IBM branded OpenPOWER system.
devtree stub.
SCU setup.
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/aspeed-bmc-opp-garrison.dts | 80 +++++++++++++++++++++++++++
arch/arm/mach-aspeed/aspeed.c | 15 +++++
3 files changed, 97 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-garrison.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9697ea5..ada1fcd 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -779,7 +779,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
dtb-$(CONFIG_MACH_OPP_PALMETTO_BMC) += \
aspeed-bmc-opp-palmetto.dtb \
- aspeed-bmc-opp-barreleye.dtb
+ aspeed-bmc-opp-barreleye.dtb \
+ aspeed-bmc-opp-garrison.dtb
endif
dtstree := $(srctree)/$(src)
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-garrison.dts b/arch/arm/boot/dts/aspeed-bmc-opp-garrison.dts
new file mode 100644
index 0000000..93c84d2
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-garrison.dts
@@ -0,0 +1,80 @@
+/dts-v1/;
+
+#include "ast2400.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Garrison BMC";
+ compatible = "ibm,garrison-bmc", "aspeed,ast2400";
+
+ ahb {
+ fmc at 1e620000 {
+ reg = < 0x1e620000 0x94
+ 0x20000000 0x02000000 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "aspeed,fmc";
+ flash at 0 {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor" ;
+ /*
+ * Possibly required props:
+ * spi-max-frequency = <>
+ * spi-tx-bus-width = <>
+ * spi-rx-bus-width = <>
+ * m25p,fast-read
+ * spi-cpol if inverse clock polarity (CPOL)
+ * spi-cpha if shifted clock phase (CPHA)
+ */
+#include "aspeed-bmc-opp-flash-layout.dtsi"
+ };
+ };
+ spi at 1e630000 {
+ reg = < 0x1e630000 0x18
+ 0x30000000 0x02000000 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "aspeed,smc";
+ flash {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor" ;
+ label = "pnor";
+ /* spi-max-frequency = <>; */
+ /* m25p,fast-read; */
+ };
+ };
+ apb {
+ i2c: i2c at 1e78a040 {
+ i2c4: i2c-bus at 140 {
+ occ at 50 {
+ compatible = "ibm,occ-i2c";
+ reg = <0x50>;
+ };
+ };
+ i2c5: i2c-bus at 180 {
+ occ at 50 {
+ compatible = "ibm,occ-i2c";
+ reg = <0x50>;
+ };
+ };
+ i2c10: i2c-bus at 3c0 {
+ status = "okay";
+ };
+ i2c11: i2c-bus at 400 {
+ status = "okay";
+
+ rtc at 68 {
+ compatible = "dallas,ds3231";
+ reg = <0x68>;
+ };
+ };
+ i2c12: i2c-bus at 440 {
+ status = "okay";
+ };
+ i2c13: i2c-bus at 480 {
+ status = "okay";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c
index 594a781..18aefdb 100644
--- a/arch/arm/mach-aspeed/aspeed.c
+++ b/arch/arm/mach-aspeed/aspeed.c
@@ -171,6 +171,18 @@ static void __init do_palmetto_setup(void)
writel(0x01C0007F, AST_IO(AST_BASE_SCU | 0x88));
}
+static void __init do_garrison_setup(void)
+{
+ do_common_setup();
+
+ /* Setup PNOR address mapping for 64M flash */
+ writel(0x30000C00, AST_IO(AST_BASE_LPC | 0x88));
+ writel(0xFC0003FF, AST_IO(AST_BASE_LPC | 0x8C));
+
+ /* SCU setup */
+ writel(0xd7000000, AST_IO(AST_BASE_SCU | 0x88));
+}
+
#define SCU_PASSWORD 0x1688A8A8
static void __init aspeed_init_early(void)
@@ -207,6 +219,9 @@ static void __init aspeed_init_early(void)
do_barreleye_setup();
if (of_machine_is_compatible("tyan,palmetto-bmc"))
do_palmetto_setup();
+ if (of_machine_is_compatible("ibm,garrison-bmc"))
+ do_garrison_setup();
+
}
static void __init aspeed_map_io(void)
--
2.8.1
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