[PATCH linux 1/2] arm/mach-aspeed: Enable UART clock divisor

[OpenBMC Patches]

From: Jeremy Kerr <jk at ozlabs.org>

Our .dts assumes that the UART clock is divided by 13, but different
u-boots may leave this bit in different states. Initialise it in
aspeed_early_init explicitly.

Signed-off-by: Jeremy Kerr <jk at ozlabs.org>
---
 arch/arm/mach-aspeed/aspeed.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c
index 64d379a..9d106b8 100644
--- a/arch/arm/mach-aspeed/aspeed.c
+++ b/arch/arm/mach-aspeed/aspeed.c
@@ -128,6 +128,8 @@ static void udbg_uart_putc(char c)
 
 static void __init aspeed_init_early(void)
 {
+	u32 reg;
+
 	// XXX UART stuff to fix to pinmux & co
 	printk("UART IO MUX...\n");
 	writel(0x02010023, AST_IO(AST_BASE_LPC | 0x9c));
@@ -137,6 +139,14 @@ static void __init aspeed_init_early(void)
 	writel(0xcb000000, AST_IO(AST_BASE_SCU | 0x80));
 	writel(0x00fff0c0, AST_IO(AST_BASE_SCU | 0x84));
 	writel(0x10CC5E80, AST_IO(AST_BASE_SCU | 0x0c));
+
+	/* We enable the UART clock divisor in the SCU's misc control
+	 * register, as the baud rates in aspeed.dtb all assume that the
+	 * divisor is active
+	 */
+	reg = readl(AST_IO(AST_BASE_SCU | 0x2c));
+	writel(reg | 0x00001000, AST_IO(AST_BASE_SCU | 0x2c));
+
 	printk("DONE, MUX=%08x %08x\n", readl(AST_IO(AST_BASE_SCU | 0x80)),
 	       readl(AST_IO(AST_BASE_SCU | 0x84)));
 	printk("CLOCK_CTRL=%08x\n", readl(AST_IO(AST_BASE_SCU)));
-- 
2.6.0