[PATCH linux 3/3] openbmc: add spi-nor to palmetto

[OpenBMC Patches]

From: "Milton D. Miller II" <miltonm at us.ibm.com>

This patch updates the openpower palmetto BMC device tree to add
a 32MB spi-nor to the static memory controller for the BMC use and
a 32MB spi-nor to the SPI memory controller for the PNOR.

The BMC nor has device tree partitions for u-boot, the uboot environment,
the kernel, and the remaining space for an initrd.  I kept the sizes
matching what the current openbmc build is making.  The current initrd
is between 16 an 17MB and 29MB is allocated.

The PNOR is given as one PNOR partition.  There is no partitioning
support in the current kernel for the ffs system used by openpower.

Signed-off-by: Milton Miller <miltonm at us.ibm.com>
---
 arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 53 +++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
index 2c3e824..79bc298 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
@@ -7,6 +7,59 @@
 	compatible = "tyan,palmetto-bmc", "aspeed,ast2400";
 
 	ahb {
+		fmc at 1e620000 {
+			reg = < 0x1e620000 0x94
+				0x20000000 0x02000000 >;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "aspeed,fmc";
+			bmc at 0 {
+				reg = < 0 >;
+				compatible = "jedec,spi-nor" ;
+				label = "bmc0";
+				/*
+				 * Possibly required props:
+				 * spi-max-frequency = <>
+				 * spi-tx-bus-width = <>
+				 * spi-rx-bus-width  = <>
+				 * m25p,fast-read
+				 * spi-cpol if inverse clock polarity (CPOL)
+				 * spi-cpha if shifted clock phase (CPHA)
+				 */
+				#address-cells = < 1 >;
+				#size-cells = < 1 >;
+				u-boot {
+					reg = < 0 0x60000 >;
+					label = "u-boot";
+				};
+				u-boot-env {
+					reg = < 0x60000 0x20000 >;
+					label = "u-boot-env";
+				};
+				kernel  {
+					reg = < 0x80000 0x280000 >;
+					label = "kernel";
+				};
+				initrd  {
+					reg = < 0x300000 0x1d00000 >;
+					label = "initrd";
+				};
+			};
+		};
+		spi at 1e630000 {
+			reg = < 0x1e630000 0x18
+				0x30000000 0x02000000 >;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "aspeed,smc";
+			pnor {
+				reg = < 0 >;
+				compatible = "jedec,spi-nor" ;
+				label = "pnor";
+				/* spi-max-frequency = <>; */
+				/* m25p,fast-read; */
+			};
+		};
 		apb {
 			i2c: i2c at 1e78a040 {
 				i2c0: i2c-bus at 40 {
-- 
2.6.3