Memory barriers and spin_unlock safety

Arjan van de Ven arjan at
Sat Mar 4 07:02:12 EST 2006

On Fri, 2006-03-03 at 16:45 +0000, David Howells wrote:
> David Howells <dhowells at> wrote:
> > 	WRITE mtx
> > 	--> implies SFENCE
> Actually, I'm not sure this is true. The AMD64 Instruction Manual's writeup of
> SFENCE implies that writes can be reordered, which sort of contradicts what
> the AMD64 System Programming Manual says.

there are 2 or 3 special instructions which do "non temporal
stores" (movntq and movnit and maybe one more). sfense is designed for

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