[PATCH 00/13] spufs fixes and cleanups

[Geoff Levand]

Paul Mackerras wrote:
> Arnd Bergmann writes:
> 
> 
>>Am Dienstag, 10. Januar 2006 21:19 schrieb Geoff Levand:
>>
>>>I didn't see the fix I sent you (also below) to stop
>>>DMA at spu context save in your latest patches. �You
>>>mentioned that Mark may cover that fix in his
>>>preemptive scheduler work. �Did he put it in a
>>>routine called earlier? �Please let me know.
>>
>>The preemptive scheduler is merged into mainline now and evidently did
>>not fix this bug. I think I confused it with some other problem that is now
>>fixed, thanks for reminding me.
>>
>>Paul, please apply this.
> 
> 
> I don't recall seeing it; Geoff, could you send it to me again with a
> nice explanation and signed-off-by?
> 
> Thanks,
> Paul.
> 

spufs: Suspend/restore MFC DMA operations at SPU context switch.

The SPE Book IV indicates that MFC DMA operations must be
suspended and restored on SPU context switch (in Step 8).

This patch adds that operation, which is missing from the
current spufs implementation.


Signed-off-by: Masato Noguchi <Masato.Noguchi at jp.sony.com>
Signed-off-by: Geoff Levand <geoffrey.levand at am.sony.com>
Acked-by: Arnd Bergmann <arndb at de.ibm.com>


Index: linux-2.6.15-cell/arch/powerpc/platforms/cell/spufs/switch.c
===================================================================
--- linux-2.6.15-cell.orig/arch/powerpc/platforms/cell/spufs/switch.c	2005-12-02 15:59:28.000000000 -0800
+++ linux-2.6.15-cell/arch/powerpc/platforms/cell/spufs/switch.c	2005-12-02 16:06:11.000000000 -0800
@@ -174,11 +174,33 @@
 	struct spu_priv2 __iomem *priv2 = spu->priv2;

 	/* Save, Step 8:
-	 *     Read and save MFC_CNTL[Ss].
+	 *     Suspend DMA and save MFC_CNTL.
 	 */
-	if (csa) {
-		csa->priv2.mfc_control_RW = in_be64(&priv2->mfc_control_RW) &
-		    MFC_CNTL_SUSPEND_DMA_STATUS_MASK;
+	switch (in_be64(&priv2->mfc_control_RW) &
+	       MFC_CNTL_SUSPEND_DMA_STATUS_MASK) {
+	case MFC_CNTL_SUSPEND_IN_PROGRESS:
+		POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
+				  MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
+				 MFC_CNTL_SUSPEND_COMPLETE);
+		/* fall through */
+	case MFC_CNTL_SUSPEND_COMPLETE:
+		if (csa) {
+			csa->priv2.mfc_control_RW =
+				in_be64(&priv2->mfc_control_RW) |
+				MFC_CNTL_SUSPEND_DMA_QUEUE;
+		}
+		break;
+	case MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION:
+		out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
+		POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
+				  MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
+				 MFC_CNTL_SUSPEND_COMPLETE);
+		if (csa) {
+			csa->priv2.mfc_control_RW =
+				in_be64(&priv2->mfc_control_RW) &
+				~MFC_CNTL_SUSPEND_DMA_QUEUE;
+		}
+		break;
 	}
 }

@@ -244,6 +266,8 @@
 		eieio();
 		csa->spu_chnldata_RW[7] = in_be64(&priv2->spu_chnldata_RW);
 		eieio();
+	} else {
+		csa->priv2.mfc_control_RW &= ~MFC_CNTL_DECREMENTER_RUNNING;
 	}
 }