Maple freezing on PCI Target-Abort

[jfaslist]

Hi,
Yes, we are going to dig into all this CPC925 and Processor Interface 
initialization.
Note that I checked that both MSR_ME and MSR_RI were set prior to 
triggering the PCI Target-Abort.

-MSR_ME: If not set the CPU will "checkstop" on a machine chaeck.
-MSR_RI: So that the exception is recoverable.

Regarding MSR_RI, this should always be set, I think?
Thanks
-jfs



Benjamin Herrenschmidt wrote:

>>-What exception vector is taking care of a DERR excp? From what I can 
>>see it seems to be the "machine check" vector. But that seems a bit 
>>drastic to me. After all this is just a PCI target abort.
>>    
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>I would expect a machine check yes.
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>>-I expect that the normal behavior would be for the kernel to send a 
>>signal termination to the user process which caused the PIO READ PCI 
>>cycle (from a previously mmap()'ed VMA address). Is it  doable on this 
>>platform?  Since a READ operation is coupled by nature, I think this is 
>>the only acceptable way.
>>    
>>
>
>It should SIGBUS except if the problem occurred in the kernel. I don't
>know why it's not doing so, maybe you are hitting an issue/errata or
>misconfiguration of the 925 ?
>
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>
>>I have tried to set the MSR[RI] bit before doing the PCI cycle, but it 
>>didn't change change anything. Also on our design we disconnect the 
>>CPC925 checkstop pin from the 970 machine check pin.(see page 39 of 
>>cpc925 user's manual). So a DERR shouldn't cause a machine check I would 
>>think.
>>
>>I realize that these questions are very H/W related but couldn't find 
>>the answer in IBM doc.
>>    
>>
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