[PATCH] ppc64: More hugepage fixes
benh at kernel.crashing.org
Tue Sep 27 13:45:12 EST 2005
> I'm curious, what's the actual bug?
> __tlbie itself doesn't seem like it would do too much differently if
> called for large or small pages because all it does is align the vaddr
No, it also passes a different second argument to the asm tlbie
instruction. It needs the value of the L bit. So we could fail to
invalidate the TLB entries.
> I don't know where it would even get an unaligned address
> from unless somebody sticks one in one of the batch->addrs.
That indeed shouldn't happen afaik.
> If the addresses are aligned, I don't see how this patch would help.
The missing L bit :)
> Or, is it required that you must sync with:
> asm volatile("eieio; tlbsync; ptesync":::"memory");
> between tlbie's of large and small pages.
No. There is also the fact that we must not allow large pages to use
tlbiel (there is a test for that too). It might actually work with more
recent CPUs but that code can't deal with that. I have some rework of
the low level code in that area that will be coming soon that addresses
it in a more generic way. This fix is the "simple" one for now.
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