Fix use of LOADBASE in merge tree

[David Gibson]

The merge-tree version of LOADBASE actually loads the whole given
address from the toc for ppc64.  The matching OFF macro adjust for
this, using an offset of 0 for ppc64, but we weren't using that in
power4_idle.

Signed-off-by: David Gibson <dwg at au1.ibm.com>

Index: working-2.6/arch/powerpc/kernel/idle_power4.S
===================================================================
--- working-2.6.orig/arch/powerpc/kernel/idle_power4.S	2005-10-13 11:09:01.000000000 +1000
+++ working-2.6/arch/powerpc/kernel/idle_power4.S	2005-10-13 12:06:03.000000000 +1000
@@ -39,13 +39,13 @@
 	 * can be cleared by CPU init after the fixups are done
 	 */
 	LOADBASE(r3,cur_cpu_spec)
-	ld	r4,cur_cpu_spec at l(r3)
+	ld	r4,OFF(cur_cpu_spec)(r3)
 	ld	r4,CPU_SPEC_FEATURES(r4)
 	andi.	r0,r4,CPU_FTR_CAN_NAP
 	beqlr
 	/* Now check if user or arch enabled NAP mode */
 	LOADBASE(r3,powersave_nap)
-	lwz	r4,powersave_nap at l(r3)
+	lwz	r4,OFF(powersave_nap)(r3)
 	cmpwi	0,r4,0
 	beqlr
 


-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/people/dgibson