[PATCH] ppc64: Fix ethernet PHY reset on iMac G5

Benjamin Herrenschmidt benh at kernel.crashing.org
Thu Mar 24 17:57:08 EST 2005


Hi !

On iMac G5, when netbooting (or causing any other ethernet activity from
within the Open Firmware environment), the PHY is put into a low power
state before booting the OS. The result is that Linux doesn't see it and
networking doesn't work.

This patch adds the ethernet PHY reset platform hook to pmac_feature.c
on ppc64 (it already is commonly used on ppc32 as lots of macs have this
same problem, so the hook definition is already there and sungem is
already calling it).

Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>

Index: linux-work/arch/ppc64/kernel/pmac_feature.c
===================================================================
--- linux-work.orig/arch/ppc64/kernel/pmac_feature.c	2005-03-15 11:56:46.000000000 +1100
+++ linux-work/arch/ppc64/kernel/pmac_feature.c	2005-03-22 15:30:32.000000000 +1100
@@ -220,6 +220,36 @@
 	return 0;
 }
 
+static long __pmac g5_eth_phy_reset(struct device_node* node, long param, long value)
+{
+	struct macio_chip* macio = &macio_chips[0];
+	struct device_node *phy;
+	int need_reset;
+
+	/*
+	 * We must not reset the combo PHYs, only the BCM5221 found in
+	 * the iMac G5.
+	 */
+	phy = of_get_next_child(node, NULL);
+	if (!phy)
+		return -ENODEV;
+	need_reset = device_is_compatible(phy, "B5221");
+	of_node_put(phy);
+	if (!need_reset)
+		return 0;
+
+	/* PHY reset is GPIO 29, not in device-tree unfortunately */
+	MACIO_OUT8(K2_GPIO_EXTINT_0 + 29,
+		   KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA);
+	/* Thankfully, this is now always called at a time when we can
+	 * schedule by sungem.
+	 */
+	msleep(10);
+	MACIO_OUT8(K2_GPIO_EXTINT_0 + 29, 0);
+
+	return 0;
+}
+
 #ifdef CONFIG_SMP
 static long __pmac g5_reset_cpu(struct device_node* node, long param, long value)
 {
@@ -306,6 +336,7 @@
 	{ PMAC_FTR_ENABLE_MPIC,		g5_mpic_enable },
 	{ PMAC_FTR_READ_GPIO,		g5_read_gpio },
 	{ PMAC_FTR_WRITE_GPIO,		g5_write_gpio },
+	{ PMAC_FTR_GMAC_PHY_RESET,	g5_eth_phy_reset },
 #ifdef CONFIG_SMP
 	{ PMAC_FTR_RESET_CPU,		g5_reset_cpu },
 #endif /* CONFIG_SMP */





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