[PATCH ] cell: enable pause(0) in cpu_idle

[Milton Miller]

On Dec 15, 2005, at 9:51 AM, Arnd Bergmann wrote:

> On Dunnersdag 15 Dezember 2005 16:26, Milton Miller wrote:
>> On Dec 15, 2005, at 12:43 AM, Paul Mackerras wrote:
>
>>>> +END_FTR_SECTION_IFSET(CPU_FTR_PAUSE_ZERO)
>>>> +	EXCEPTION_PROLOG_COMMON(0x100, PACA_EXGEN);
>>>> +	b	fast_exception_return
>>>
>>> This is a change in behaviour from before the patch.  Instead of 
>>> doing
>>> the EXCEPTION_PROLOG_COMMON and then just returning, you should 
>>> branch
>>> to system_reset_common.
>>>
>>
>> Actually, this is not the case, as this is only for the MSR_WAKEMT
>> case -- they put a bne to the old handler.
>
> No, The change that Paul is referring to is for the case where
> CPU_FTR_PAUSE_ZERO is not set. I broke this when I tried to simplify
> the branches according to your comments. I now have in there
>
> BEGIN_FTR_SECTION
> ­·······mr­·····r10,r12    /* r12 has SRR1 saved */
> ­·······srwi­···r10,r10,16
> ­·······andi.­··r10,r10,MSR_WAKEMASK
> ­·······cmpwi­··r10,MSR_WAKEEE
> ­·······beq­····hardware_interrupt_common
> ­·······cmpwi­··r10,MSR_WAKEDEC
> ­·······beq­····decrementer_common
> ­·······cmpwi­··r10,MSR_WAKEMT
> ­·······bne­····system_reset_common
> ­·······EXCEPTION_PROLOG_COMMON(0x100, PACA_EXGEN);
> ­·······b­······fast_exception_return
> END_FTR_SECTION_IFSET(CPU_FTR_PAUSE_ZERO)
> ­·······b­······system_reset_common
>
> Is there a simpler way to express this?

Original patch:
>>>> +/* Wake Events */
>>>> +#define MSR_WAKEMASK	0x0038
>>>> +#define MSR_WAKERESET	0x0038
>>>> +#define MSR_WAKESYSERR	0x0030
>>>> +#define MSR_WAKEEE	0x0020
>>>> +#define MSR_WAKEMT	0x0028
>>>> +#define MSR_WAKEDEC	0x0018
>>>> +#define MSR_WAKETHERM	0x0010


You could move the unconditional branch to system_reset_common to the 
front under IFCLR (in case EXCEPTION_PROLOG wants to use it in the 
future) at the cost of adding one nop to your path.

You are looking for 3 values out of 8, and they have few bits in common 
to do a tree branch.   You could rotate left 25, move to cr0, then 
write the branch tree; not sure if it would be faster.  It would save 
the andi. and repeated compares writing the cr field, which might help 
if it is not renamed.  (I assume you want EE and DEC to be fastest).

Oh, I missed the right shift 16 in front of that, might help more.

Actually, this means the constants are wrong.  Add the 16 bits of zero 
at the end and use @h in the asm?  Or rename from MSR_ namespace (and I 
would guess they are actually SRR1 only).

Regardless, there is no reason to do mr then shift as two operations.


milton