[PATCH ] cell: enable pause(0) in cpu_idle
Max Aguilar
maguilar at us.ibm.com
Thu Dec 15 07:13:02 EST 2005
This looks good to me, thanks for looking over the code.
Max Aguilar
Linux Kernel/Bootloader/Bring-Up
STI Design Center
(512) 838-5704 T/L 678-5704
maguilar at us.ibm.com
Arnd Bergmann <arnd at arndb.de> on 12/14/2005 12:10:18 PM
To: linuxppc64-dev at ozlabs.org
cc: Milton Miller <miltonm at bga.com>, Paul Mackerras <paulus at samba.org>,
Max Aguilar/Austin/IBM at IBMUS
Subject: [PATCH ] cell: enable pause(0) in cpu_idle
This patch enables support for pause(0) power management state
for the Cell Broadband Processor, which is import for power efficient
operation. The pervasive infrastructure will in the future enable
us to introduce more functionality specific to the Cell's
pervasive unit.
This version contains more changes according to comments from Milton.
More importantly, it now also works on DD2 hardware, after I have
fixed a bug in the initialization sequence.
From: Maximino Aguilar <maguilar at us.ibm.com>
Signed-off-by: Arnd Bergmann <arndb at de.ibm.com>
---
Paul, please merge this once Milton and Max have both acknowledged
the contents.
Max, I haven't gotten any reply from you on this patch so far.
Please tell us if the changes I have done to your code look
right!
Index: linux-2.6.15-rc/arch/powerpc/platforms/cell/Makefile
===================================================================
--- linux-2.6.15-rc.orig/arch/powerpc/platforms/cell/Makefile
+++ linux-2.6.15-rc/arch/powerpc/platforms/cell/Makefile
@@ -1,4 +1,6 @@
obj-y += interrupt.o iommu.o setup.o
spider-pic.o
+obj-y += pervasive.o
+
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_SPU_FS) += spufs/ spu_base.o
builtin-spufs-$(CONFIG_SPU_FS) += spu_syscalls.o
Index: linux-2.6.15-rc/arch/powerpc/platforms/cell/pervasive.c
===================================================================
--- /dev/null
+++ linux-2.6.15-rc/arch/powerpc/platforms/cell/pervasive.c
@@ -0,0 +1,192 @@
+/*
+ * CBE Pervasive Monitor and Debug
+ *
+ * (C) Copyright IBM Corporation 2005
+ *
+ * Authors: Maximino Aguilar (maguilar at us.ibm.com)
+ * Michael N. Day (mnday at us.ibm.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#undef DEBUG
+
+#include <linux/config.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/percpu.h>
+#include <linux/types.h>
+#include <linux/kallsyms.h>
+
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/prom.h>
+#include <asm/pgtable.h>
+#include <asm/reg.h>
+
+#include "pervasive.h"
+
+struct cbe_pervasive {
+ struct pmd_regs __iomem *regs;
+ unsigned int thread;
+};
+
+/* can't use per_cpu from setup_arch */
+static struct cbe_pervasive cbe_pervasive[NR_CPUS];
+
+static void __init cbe_enable_pause_zero(void)
+{
+ unsigned long thread_switch_control;
+ unsigned long temp_register;
+ struct cbe_pervasive *p;
+ int thread;
+
+ p = &cbe_pervasive[get_cpu()];
+
+ if (!cbe_pervasive->regs)
+ return;
+
+ pr_debug("Power Management: CPU %d\n", smp_processor_id());
+
+ /* Enable Pause(0) control bit */
+ temp_register = in_be64(&p->regs->pm_control);
+
+ out_be64(&p->regs->pm_control,
+ temp_register|PMD_PAUSE_ZERO_CONTROL);
+
+ /* Enable DEC and EE interrupt request */
+ thread_switch_control = mfspr(SPRN_TSC_CELL);
+ thread_switch_control |= TSC_CELL_EE_ENABLE |
TSC_CELL_EE_BOOST;
+
+ switch ((mfspr(SPRN_CTRLF) & CTRL_CT)) {
+ case CTRL_CT0:
+ thread_switch_control |= TSC_CELL_DEC_ENABLE_0;
+ thread = 0;
+ break;
+ case CTRL_CT1:
+ thread_switch_control |= TSC_CELL_DEC_ENABLE_1;
+ thread = 1;
+ break;
+ default:
+ printk(KERN_WARNING "%s: unknown configuration\n",
+ __FUNCTION__);
+ thread = -1;
+ break;
+ }
+
+ if (p->thread != thread)
+ printk(KERN_WARNING "%s: device tree inconsistant,
"
+ "cpu %i: %d/%d\n",
__FUNCTION__,
+ smp_processor_id(),
+ p->thread, thread);
+
+ mtspr(SPRN_TSC_CELL, thread_switch_control);
+
+ put_cpu();
+}
+
+static void cbe_idle(void)
+{
+ unsigned long ctrl;
+
+ cbe_enable_pause_zero();
+
+ while (1) {
+ if (!need_resched()) {
+ while (!need_resched()) {
+ /* go into low thread
priority */
+ HMT_low();
+
+ /* go into low power mode
*/
+ local_irq_disable();
+ ctrl = mfspr(SPRN_CTRLF);
+ ctrl &= ~(CTRL_RUNLATCH |
CTRL_TE);
+ mtspr(SPRN_CTRLT, ctrl);
+ local_irq_enable();
+ }
+ /* restore thread prio */
+ HMT_medium();
+ }
+
+ ppc64_runlatch_on();
+ preempt_enable_no_resched();
+ schedule();
+ preempt_disable();
+ }
+}
+
+static int __init cbe_find_pmd_mmio(int cpu, struct cbe_pervasive *p)
+{
+ struct device_node *node;
+ unsigned int *int_servers;
+ char *addr;
+ unsigned long real_address;
+ unsigned int size;
+
+ struct pmd_regs __iomem *pmd_mmio_area;
+ int hardid, thread;
+ int proplen;
+
+ pmd_mmio_area = NULL;
+ hardid = get_hard_smp_processor_id(cpu);
+ for (node = NULL; (node = of_find_node_by_type(node, "cpu"));)
{
+ int_servers = (void *) get_property(node,
+
"ibm,ppc-interrupt-server#s", &proplen);
+ if (!int_servers) {
+ printk(KERN_WARNING "CPU device misses
"
+
"ibm,ppc-interrupt-server#s property");
+ continue;
+ }
+ for (thread = 0; thread < proplen / sizeof (int);
thread++) {
+ if (hardid == int_servers[thread]) {
+ addr = get_property(node,
"pervasive", NULL);
+ goto found;
+ }
+ }
+ }
+
+ printk(KERN_WARNING "%s: CPU %d not found\n", __FUNCTION__,
cpu);
+ return -EINVAL;
+
+found:
+ real_address = *(unsigned long*) addr;
+ addr += sizeof (unsigned long);
+ size = *(unsigned int*) addr;
+
+ pr_debug("pervasive area for CPU %d at %lx, size %x\n",
+ cpu, real_address, size);
+ p->regs = __ioremap(real_address, size, _PAGE_NO_CACHE);
+ p->thread = thread;
+ return 0;
+}
+
+void __init cell_pervasive_init(void)
+{
+ struct cbe_pervasive *p;
+ int cpu;
+ int ret;
+
+ if (!cpu_has_feature(CPU_FTR_PAUSE_ZERO))
+ return;
+
+ for_each_cpu(cpu) {
+ p = &cbe_pervasive[cpu];
+ ret = cbe_find_pmd_mmio(cpu, p);
+ if (ret)
+ return;
+ }
+
+ ppc_md.idle_loop = cbe_idle;
+}
Index: linux-2.6.15-rc/arch/powerpc/platforms/cell/pervasive.h
===================================================================
--- /dev/null
+++ linux-2.6.15-rc/arch/powerpc/platforms/cell/pervasive.h
@@ -0,0 +1,62 @@
+/*
+ * Cell Pervasive Monitor and Debug interface and HW structures
+ *
+ * (C) Copyright IBM Corporation 2005
+ *
+ * Authors: Maximino Aguilar (maguilar at us.ibm.com)
+ * David J. Erb (djerb at us.ibm.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+
+#ifndef PERVASIVE_H
+#define PERVASIVE_H
+
+struct pmd_regs {
+ u8 pad_0x0000_0x0800[0x0800 - 0x0000];
/* 0x0000 */
+
+ /* Thermal Sensor Registers */
+ u64 ts_ctsr1;
/* 0x0800 */
+ u64 ts_ctsr2;
/* 0x0808 */
+ u64 ts_mtsr1;
/* 0x0810 */
+ u64 ts_mtsr2;
/* 0x0818 */
+ u64 ts_itr1;
/* 0x0820 */
+ u64 ts_itr2;
/* 0x0828 */
+ u64 ts_gitr;
/* 0x0830 */
+ u64 ts_isr;
/* 0x0838 */
+ u64 ts_imr;
/* 0x0840 */
+ u64 tm_cr1;
/* 0x0848 */
+ u64 tm_cr2;
/* 0x0850 */
+ u64 tm_simr;
/* 0x0858 */
+ u64 tm_tpr;
/* 0x0860 */
+ u64 tm_str1;
/* 0x0868 */
+ u64 tm_str2;
/* 0x0870 */
+ u64 tm_tsr;
/* 0x0878 */
+
+ /* Power Management */
+ u64 pm_control;
/* 0x0880 */
+#define PMD_PAUSE_ZERO_CONTROL 0x10000
+ u64 pm_status;
/* 0x0888 */
+
+ /* Time Base Register */
+ u64 tbr;
/* 0x0890 */
+
+ u8 pad_0x0898_0x1000 [0x1000 - 0x0898];
/* 0x0898 */
+};
+
+void __init cell_pervasive_init(void);
+
+#endif
Index: linux-2.6.15-rc/arch/powerpc/platforms/cell/setup.c
===================================================================
--- linux-2.6.15-rc.orig/arch/powerpc/platforms/cell/setup.c
+++ linux-2.6.15-rc/arch/powerpc/platforms/cell/setup.c
@@ -49,6 +49,7 @@
#include "interrupt.h"
#include "iommu.h"
+#include "pervasive.h"
#ifdef DEBUG
#define DBG(fmt...) udbg_printf(fmt)
@@ -165,6 +166,7 @@ static void __init cell_setup_arch(void)
init_pci_config_tokens();
find_and_init_phbs();
spider_init_IRQ();
+ cell_pervasive_init();
#ifdef CONFIG_DUMMY_CONSOLE
conswitchp = &dummy_con;
#endif
Index: linux-2.6.15-rc/arch/powerpc/kernel/head_64.S
===================================================================
--- linux-2.6.15-rc.orig/arch/powerpc/kernel/head_64.S
+++ linux-2.6.15-rc/arch/powerpc/kernel/head_64.S
@@ -401,7 +401,7 @@ label##_common:
\
.globl __start_interrupts
__start_interrupts:
- STD_EXCEPTION_PSERIES(0x100, system_reset)
+ STD_EXCEPTION_PSERIES(0x100, system_reset_check)
. = 0x200
_machine_check_pSeries:
@@ -880,6 +880,28 @@ unrecov_fer:
bl .unrecoverable_exception
b 1b
+/* This is a new system reset handler for the BE processor.
+ * SRR1 stores wake information that must be decoded to determine why
+ * the processor was at the system reset handler.
+ */
+
+ .align 7
+ .globl system_reset_check_common
+system_reset_check_common:
+BEGIN_FTR_SECTION
+ mr r22,r12 /* r12 has SRR1 saved */
+ srwi r22,r22,16
+ andi. r22,r22,MSR_WAKEMASK
+ cmpwi r22,MSR_WAKEEE
+ beq hardware_interrupt_common
+ cmpwi r22,MSR_WAKEDEC
+ beq decrementer_common
+ cmpwi r22,MSR_WAKEMT
+ bne system_reset_common
+END_FTR_SECTION_IFSET(CPU_FTR_PAUSE_ZERO)
+ EXCEPTION_PROLOG_COMMON(0x100, PACA_EXGEN);
+ b fast_exception_return
+
/*
* Here r13 points to the paca, r9 contains the saved CR,
* SRR0 and SRR1 are saved in r11 and r12,
Index: linux-2.6.15-rc/include/asm-powerpc/cputable.h
===================================================================
--- linux-2.6.15-rc.orig/include/asm-powerpc/cputable.h
+++ linux-2.6.15-rc/include/asm-powerpc/cputable.h
@@ -106,6 +106,7 @@ extern void do_cpu_ftr_fixups(unsigned l
#define CPU_FTR_LOCKLESS_TLBIE
ASM_CONST(0x0000040000000000)
#define CPU_FTR_MMCRA_SIHV
ASM_CONST(0x0000080000000000)
#define CPU_FTR_CI_LARGE_PAGE
ASM_CONST(0x0000100000000000)
+#define CPU_FTR_PAUSE_ZERO
ASM_CONST(0x0000200000000000)
#else
/* ensure on 32b processors the flags are available for compiling but
* don't do anything */
@@ -305,7 +306,8 @@ enum {
CPU_FTR_MMCRA_SIHV,
CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT,
+ CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT |
+ CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO,
CPU_FTRS_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB
|
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2,
#endif
Index: linux-2.6.15-rc/include/asm-powerpc/reg.h
===================================================================
--- linux-2.6.15-rc.orig/include/asm-powerpc/reg.h
+++ linux-2.6.15-rc/include/asm-powerpc/reg.h
@@ -92,6 +92,15 @@
#define MSR_RI __MASK(MSR_RI_LG) /*
Recoverable Exception */
#define MSR_LE __MASK(MSR_LE_LG) /*
Little Endian */
+/* Wake Events */
+#define MSR_WAKEMASK 0x0038
+#define MSR_WAKERESET 0x0038
+#define MSR_WAKESYSERR 0x0030
+#define MSR_WAKEEE 0x0020
+#define MSR_WAKEMT 0x0028
+#define MSR_WAKEDEC 0x0018
+#define MSR_WAKETHERM 0x0010
+
#ifdef CONFIG_PPC64
#define MSR_ MSR_ME | MSR_RI | MSR_IR | MSR_DR |
MSR_ISF
#define MSR_KERNEL MSR_ | MSR_SF | MSR_HV
@@ -145,6 +154,10 @@
#define SPRN_CTR 0x009 /* Count Register */
#define SPRN_CTRLF 0x088
#define SPRN_CTRLT 0x098
+#define CTRL_CT 0xc0000000 /* current thread */
+#define CTRL_CT0 0x80000000 /* thread 0 */
+#define CTRL_CT1 0x40000000 /* thread 1 */
+#define CTRL_TE 0x00c00000 /* thread enable */
#define CTRL_RUNLATCH 0x1
#define SPRN_DABR 0x3F5 /* Data Address Breakpoint
Register */
#define DABR_TRANSLATION (1UL << 2)
@@ -257,11 +270,11 @@
#define SPRN_HID6 0x3F9 /* BE HID 6 */
#define HID6_LB (0x0F<<12) /* Concurrent Large Page
Modes */
#define HID6_DLP (1<<20) /* Disable all large
page modes (4K only) */
-#define SPRN_TSCR 0x399 /* Thread switch control on BE
*/
-#define SPRN_TTR 0x39A /* Thread switch timeout on BE
*/
-#define TSCR_DEC_ENABLE 0x200000 /* Decrementer
Interrupt */
-#define TSCR_EE_ENABLE 0x100000 /* External Interrupt
*/
-#define TSCR_EE_BOOST 0x080000 /* External
Interrupt Boost */
+#define SPRN_TSC_CELL 0x399 /* Thread
switch control on Cell */
+#define TSC_CELL_DEC_ENABLE_0 0x400000 /*
Decrementer Interrupt */
+#define TSC_CELL_DEC_ENABLE_1 0x200000 /*
Decrementer Interrupt */
+#define TSC_CELL_EE_ENABLE 0x100000 /* External
Interrupt */
+#define TSC_CELL_EE_BOOST 0x080000 /* External
Interrupt Boost */
#define SPRN_TSC 0x3FD /* Thread switch
control on others */
#define SPRN_TST 0x3FC /* Thread switch
timeout on others */
#if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
Index: linux-2.6.15-rc/arch/powerpc/kernel/cputable.c
===================================================================
--- linux-2.6.15-rc.orig/arch/powerpc/kernel/cputable.c
+++ linux-2.6.15-rc/arch/powerpc/kernel/cputable.c
@@ -273,7 +273,7 @@ struct cpu_spec cpu_specs[] = {
.oprofile_model =
&op_model_power4,
#endif
},
- { /* BE DD1.x */
+ { /* Cell Broadband Engine */
.pvr_mask = 0xffff0000,
.pvr_value = 0x00700000,
.cpu_name = "Cell Broadband
Engine",
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