PCI Error Recovery API Proposal (updated)

[Grant Grundler]

On Tue, Apr 12, 2005 at 09:56:40AM +1000, Benjamin Herrenschmidt wrote:
...
> I would appreciate if other people following this discussion could give
> their opinion here, just to make sure I'm not following the wrong track.
> But it seems to me that issuing the request for a link reset doesn't fit
> in the leaf driver recovery API, but rather in the private API that you
> will define between the PCI Express error recovery core and the PCI
> Express port drivers...

I *think* you are on the right track.

Device drivers must know a little bit about which type of bus they
are on because of probe (how driver is bound to device).  AFAIK,
Power control (suspend/resume and hotplug) and interrupt handling (MSI/MSI-X)
have managed to abstract out bus specifics. I expect the link reset
could be abstracted as well.

(e.g could one suspend and resume an EISA driver?
 Probably with some tweaking.)

In general, the less drivers know about bus, the more portable
they are to other chipset/architectures. But that hasn't stopped driver
writers from mucking with things like cacheline size, Latency timer,
or MMRBC (PCI-X).

I warn this because several of the PCIe cards I'm aware of use
a PCIe-to-PCI-X bridge to make a PCI-X device work in a PCIe slot.
ie, it's really a PCI-X device that knows nothing about the PCI-e
that's upstream. Error recovery is going to be very .... "interesting"
to support for those devices.

grant