Booting Imac G5

[Benjamin Herrenschmidt]

> OK, my mistake...
> I forgot one point: I was using 2.6.10-rc2 while my previous tests were
> with 2.6.10-rc1.
> So it seems the bug was corrected between those two pre-release. Great !
> 
> For your information, here are some registers dumps:
> PVR: 003c0300 MSR: 9000000000009032 PIR: 00000000
> HID0: 0051108100000000 HID1: fd3c200000000000
> HID4: 0000001000000000 HID5: 0000000000000000
> 
> For the SMU driver I need a function that uses dcbf, because we send a
> buffer address to the SMU and the chip may modify this buffer. So I now
> added another helper, like flush_dcache_phys_range but using dcbf
> instead of dcbst.

Why ? dcbst should work as well... I use flush_dcache_phys_range() for
the IOMMU without problem so far...

> > In addition, the L1 D cache of the 970 is write-through, so it should
> > never contain dirty data anyway... so neither dcbf nor dcbst is strictly
> > necessary, provided we have a sync before the icbi afaik ...
> 
> Well, don't we still need dcbst to flush the L2 cache ?

Not for flush_icache_dcache (that is I/D cache coherency) since only the
L1 cache is split.

> Furthermore, in flush_dcache_range & flush_dcache_phys_range, I can see
> no icbi and I don't see why we should have one, as the thing is to flush
> data cache, not icache.

They are mean't for a different purpose, which is to sync with
non-coherent DMA devices, like the IOMMU (I'm not sure you actually need
something like that for the SPU, normally, the northbridge should take
care of coherency ...)

Ben.