[PATCH][2.6] Nested Interrupt support

[Anton Blanchard]

Hi Jake,

> The xics code is not behaving completly correct.  When a hw interrupt is
> taken the CPPR is changed to 0x5.  If while this interrupt is being
> processed, the CPU gets interrupted with a higher priority interrupt (eg
> IPI), the IPI's EOI will write the CPPR back down to 0xFF instead of
> what it was at when it interrupted the hw interrupt (0x5).

Looks good. Could we use per cpu data here (do we init per cpu data
before the xics setup)? Also Im wondering if we should have a quick
check for overflow of the buffer.

> One concern I have is at the end of ppc_irq_dispatch_handler(), there is
> a check to see if the desc->handler went away due to an interrupt being
> disabled.  If the handler does go away, desc->handler->end will not be
> called and the irq_stack will get out of sync.  I could not find
> anywhere were this handler would actually be removed (eg function
> pointer set to zero).  Why is this code still here?

Im not sure, how does it match up with what x86 does these days?

Anton

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