[PATCH] sparse fixes for cpu feature constants
Nathan Lynch
nathanl at austin.ibm.com
Thu Dec 30 15:33:26 EST 2004
Hi-
I've been playing around with sparse a little and saw that it gives a
lot of warnings like this:
arch/ppc64/mm/init.c:755:35: warning: constant 0x0000020000000000 is so
big it is long
It looks like we get such a warning for every expression of the form
"(cur_cpu_spec->cpu_features & CPU_FTR_COHERENT_ICACHE)" -- basically,
every time the code checks for a cpu feature.
Following is an attempt to clean these up by defining the cpu feature
constants using the ASM_CONST macro from ppc64's page.h. I believe this
is consistent with the intentions for ASM_CONST's use.
There's some fallout:
flush_icache_range() was already using ASM_CONST on one of the
constants, so that is fixed up.
switch_mm() uses a BEGIN_FTR_SECTION ...
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) which gets broken by the change
since 0x0000000000000008UL winds up in the generated assembly. I
couldn't find the BEGIN/END_FTR_SECTION construct used in any other C
code, so I replaced this with the usual bitwise 'and' conditional (I
hope someone else will verify that this is equivalent :).
So, does this look like the right thing to do? It eliminates 129 sparse
warnings from a defconfig 2.6.10 build.
Signed-off-by: Nathan Lynch <nathanl at austin.ibm.com>
Index: 2.6.10/include/asm-ppc64/cputable.h
===================================================================
--- 2.6.10.orig/include/asm-ppc64/cputable.h 2004-12-24 21:35:23.000000000 +0000
+++ 2.6.10/include/asm-ppc64/cputable.h 2004-12-30 04:04:09.463979408 +0000
@@ -16,6 +16,7 @@
#define __ASM_PPC_CPUTABLE_H
#include <linux/config.h>
+#include <asm/page.h> /* for ASM_CONST */
/* Exposed to userland CPU features - Must match ppc32 definitions */
#define PPC_FEATURE_32 0x80000000
@@ -103,38 +104,38 @@
/* CPU kernel features */
/* Retain the 32b definitions for the time being - use bottom half of word */
-#define CPU_FTR_SPLIT_ID_CACHE 0x0000000000000001
-#define CPU_FTR_L2CR 0x0000000000000002
-#define CPU_FTR_SPEC7450 0x0000000000000004
-#define CPU_FTR_ALTIVEC 0x0000000000000008
-#define CPU_FTR_TAU 0x0000000000000010
-#define CPU_FTR_CAN_DOZE 0x0000000000000020
-#define CPU_FTR_USE_TB 0x0000000000000040
-#define CPU_FTR_604_PERF_MON 0x0000000000000080
-#define CPU_FTR_601 0x0000000000000100
-#define CPU_FTR_HPTE_TABLE 0x0000000000000200
-#define CPU_FTR_CAN_NAP 0x0000000000000400
-#define CPU_FTR_L3CR 0x0000000000000800
-#define CPU_FTR_L3_DISABLE_NAP 0x0000000000001000
-#define CPU_FTR_NAP_DISABLE_L2_PR 0x0000000000002000
-#define CPU_FTR_DUAL_PLL_750FX 0x0000000000004000
+#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
+#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
+#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
+#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
+#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
+#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
+#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
+#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
+#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
+#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
+#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
+#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
+#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
+#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
+#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
/* Add the 64b processor unique features in the top half of the word */
-#define CPU_FTR_SLB 0x0000000100000000
-#define CPU_FTR_16M_PAGE 0x0000000200000000
-#define CPU_FTR_TLBIEL 0x0000000400000000
-#define CPU_FTR_NOEXECUTE 0x0000000800000000
-#define CPU_FTR_NODSISRALIGN 0x0000001000000000
-#define CPU_FTR_IABR 0x0000002000000000
-#define CPU_FTR_MMCRA 0x0000004000000000
-#define CPU_FTR_PMC8 0x0000008000000000
-#define CPU_FTR_SMT 0x0000010000000000
-#define CPU_FTR_COHERENT_ICACHE 0x0000020000000000
-#define CPU_FTR_LOCKLESS_TLBIE 0x0000040000000000
-#define CPU_FTR_MMCRA_SIHV 0x0000080000000000
+#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
+#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
+#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
+#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
+#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000)
+#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
+#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
+#define CPU_FTR_PMC8 ASM_CONST(0x0000008000000000)
+#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
+#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
+#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
+#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
/* Platform firmware features */
-#define FW_FTR_ 0x0000000000000001
+#define FW_FTR_ ASM_CONST(0x0000000000000001)
#ifndef __ASSEMBLY__
#define COMMON_USER_PPC64 (PPC_FEATURE_32 | PPC_FEATURE_64 | \
Index: 2.6.10/include/asm-ppc64/cacheflush.h
===================================================================
--- 2.6.10.orig/include/asm-ppc64/cacheflush.h 2004-12-24 21:33:51.000000000 +0000
+++ 2.6.10/include/asm-ppc64/cacheflush.h 2004-12-30 04:00:42.928965272 +0000
@@ -40,7 +40,7 @@
static inline void flush_icache_range(unsigned long start, unsigned long stop)
{
- if (!(cur_cpu_spec->cpu_features & ASM_CONST(CPU_FTR_COHERENT_ICACHE)))
+ if (!(cur_cpu_spec->cpu_features & CPU_FTR_COHERENT_ICACHE))
__flush_icache_range(start, stop);
}
Index: 2.6.10/include/asm-ppc64/mmu_context.h
===================================================================
--- 2.6.10.orig/include/asm-ppc64/mmu_context.h 2004-12-24 21:34:31.000000000 +0000
+++ 2.6.10/include/asm-ppc64/mmu_context.h 2004-12-30 04:00:42.000000000 +0000
@@ -52,11 +52,8 @@
struct task_struct *tsk)
{
#ifdef CONFIG_ALTIVEC
- asm volatile (
- BEGIN_FTR_SECTION
- "dssall;\n"
- END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
- : : );
+ if (cur_cpu_spec->cpu_features & CPU_FTR_ALTIVEC)
+ asm volatile ("dssall;\n" : : );
#endif /* CONFIG_ALTIVEC */
if (!cpu_isset(smp_processor_id(), next->cpu_vm_mask))
More information about the Linuxppc64-dev
mailing list