icache coherency

[Anton Blanchard]

Hi,

Ive been playing with the cache flush avoidance code, looking for
areas we can optimise. The first obvious area is to avoid flushing
the icache after a COW fault when the VMA is not marked executable.

Unfortunately we cannot for a few reasons:

1. The ppc32 ABI has a blrl instruction in the word before the start
of the GOT. The aim here is to be able to calculate the address of the
GOT by doing:

	bl GOT-4
	mflr r30

Unfortunately the segment with the blrl is not always marked executable.
Alan Modra just fixed this in binutils but there are an awful number of
binaries and libraries out there with this problem.

2. The PLT was not always marked executable. More bad news.


Ive put together workarounds in ld.so and the kernel that get around
these two problems, but it doesnt help us much performance wise (I have
to mark the entire data section executable and we end up syncing the
icache on COW faults for all executables and libraries.)

Anton

** Sent via the linuxppc64-dev mail list. See http://lists.linuxppc.org/