Problem with flush_icache_range, linux-2.6.27-rc7-denx & mpc8270

[Remi Lefevre]

Hello,

I'm new to PowerPC and encounter some problems booting Linux on a custom
MPC8270 board.

The boot sequence goes wrong at the begining of the MMU init, in MMU_init_hw().

[arch/powerpc/mm/ppc_mmu_32.c]
...
    if (!cpu_has_feature(CPU_FTR_HPTE_TABLE)) {
        /*
         * Put a blr (procedure return) instruction at the
         * start of hash_page, since we can still get DSI
         * exceptions on a 603.
         */
        hash_page[0] = 0x4e800020;
        flush_icache_range((unsigned long) &hash_page[0],      <- Never returns
                   (unsigned long) &hash_page[1]);
        return;
    }
...

the problem in flush_icache_range occurs when the first cache block is copied
to memory, at dcbst instruction:

[arch/powerpc/kernel/misc_32.S]
...
_KPROBE(__flush_icache_range)
BEGIN_FTR_SECTION
    blr             /* for 601, do nothing */
END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
    li  r5,L1_CACHE_BYTES-1
    andc    r3,r3,r5
    subf    r4,r3,r4
    add r4,r4,r5
    srwi.   r4,r4,L1_CACHE_SHIFT
    beqlr
    mtctr   r4
    mr  r6,r3
1:  dcbst   0,r3                                  <- Control is lost here
    addi    r3,r3,L1_CACHE_BYTES
    bdnz    1b
    sync
...

By stepping, I lose debugger control at this point. No exception seems to
occur.  No more log is stored in the log buffer. The instruction seems to
never end.

L1_CACHE_BYTES has the value (1 << 5), corresponding the CONFIG_PPC32
config.

R0    00030040
R1    C0311FC0
R2    C02F7578
R3    C0014B20
R4           1
R5          1F
R6    C031B456
R7    C0320000


Any idea on possible causes or ways to improve my investigations would be
greatly appreciated.

Best regards,
Rémi Lefevre

---

Versions:

(U-Boot 1.3.4)
linux-2.6-denx.git from today
(linux-2.6-denx-63646fc60b177cfc511d8d35a9134902f41f9898)

Kernel configuration is identical to pq2fads:

CONFIG_6xx=y
CONFIG_PPC_FPU=y
CONFIG_PPC_STD_MMU=y
CONFIG_PPC_STD_MMU_32=y
CONFIG_PPC32=y
CONFIG_WORD_SIZE=32
CONFIG_PPC_MERGE=y
CONFIG_MMU=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_IRQ_PER_CPU=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_ARCH_HAS_ILOG2_U32=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_PPC=y
CONFIG_EARLY_PRINTK=y
CONFIG_GENERIC_NVRAM=y
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_PPC_OF=y
CONFIG_OF=y
CONFIG_AUDIT_ARCH=y
CONFIG_GENERIC_BUG=y
CONFIG_DEFAULT_UIMAGE=y