MPC5200B SPI codec error when there is a heavy ethernet

Juergen Beisert jbe at
Mon Jan 28 20:33:40 EST 2008

On Monday 28 January 2008 09:37, TXEMA LOPEZ wrote:
> The engineers of Freescale have recognized a problem in the PSC SPI Slave
> Select signal when there is a heavy ethernet loading. Textually they say:
> " I have tested the MPC5200B FEC and PSC6 SPI.
> You are right. If there is heavy Ethernet loading, the PSC SPI can stop
> during transmission with SS goes high. Use a general-purpose output as SPI
> slave select signal instead PSC SPI SS signal. Factory is informed about
> similar incorrect behaviour of the PSC SPI slave select."
> We have repeated the error in three scenarios:
> 	In our MPC5200B custom board with a Denx 2.4.25 kernel.
> 	In a Lite5200B with a Denx 2.4.25 kernel.
> 	In a Lite5200B with the freescale bsp:
> mpc5200_lite5200b_20070203_ltib-rc4. It's a 2.6.16 kernel version.
> We have checked the PSC3 and PSC6 and the behaviour is the same.
> So, it seems is a chip's bug and we must avoid to use the SS signal with
> the PSC SPI if we want to communicate by ethernet. I think it's a
> probabilistic error and in case there is some traffic in ethernet and a
> transmission by SPI at the same time it could happen.

There seems also another bug: If the PSC based SPI unit runs as SPI slave, and 
some data in the send FIFO waits for transmission, the MISO line is active 
even if SS input is high and blocks the bus. It does not happen, of the send 
FIFO is empty.

Dipl.-Ing. Juergen Beisert |
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