Problems of using APU/FPU under linux

Stephen Neuendorffer stephen.neuendorffer at
Tue Apr 15 03:35:24 EST 2008

I'm not sure exactly what's going on here.  Generally speaking, if you
have the FPU instantiated in the design and enable the APU in the msr,
then the processor should decode FP instructions and send them directly
to the APU with no trap.  I haven't done this myself, or I could
probably give you some better help...

One thing you should be aware of is that the there are gcc compiler
patches which are necessary to get the FPU working properly.  However, I
don't think the failure mode that these patches workaround would cause a
trap, so my guess is that there is still something else wrong.


> -----Original Message-----
> From: at
> at] On Behalf Of Shanyuan
> Sent: Monday, April 14, 2008 9:18 AM
> To: linuxppc-embedded at
> Subject: Problems of using APU/FPU under linux
> Hi,
> Recently I was trying to make APU/FPU working under Linux on Xilinx
> ML410. The standalone programs work perfectly. However under Linux,
> when I try to use a floating point operation, like *fmuls*, it will
> give me a *trap*.
> By studying the user guide from Xilinx and dumping the object files,
> I know I need to change the corresponding bits (APU enable, FP
> enable, maybe APU Exception enable) in Machine State Register. I
> guess I need to enable the bits whenever before the kernel uses
> *mtmsr*. However, it doesn't work. I got the same trap with the same
> MSR, as I had no APU/FPU before. I also tried to add the FPU.S to ppc
> tree, but it doesn't work either.
> The questions are
> 1. I guess there might be some place that changed MSR after all my
> changes. But I don't know where. And can I write a kernel module to
> change the MSR after booting in Linux? (well, it's hard for me though)
> 2. Does it have any exception/interrupt mechanism to direct FP
> operation to APU/FPU? Or after enabling APU/FPU it will mask the
> exception/interrupt and decode FP operation by itself?
> Any ideas are appreciated. Thank you very much!
> Shan
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