PCI target implementation on AMCC PPC CPUs

[David Hawkins]

Hi Matthias,

> we build a couple of PCI target designs using AMCC PowerPCs.
> You are right that some things could be better. But ..
> 
> On Thursday 06 September 2007 22:26, David Hawkins wrote:
>> There are several fundamental problems with the AMCC 440EP
>> acting as a PCI target/slave;
>>
>> 2. Look in the data sheet and see if you can figure out
>>     how the host processor can generate an interrupt to
>>     the PowerPC core ... oops, you can't. That kind of
>>     makes it difficult to work with doesn't it.
>
> You CAN! You can generate an interrupt to the PowerPC from the host
> CPU bei writing to the PCI command register. You have to read the user manual
> carefully. Perhaps it not that obvious.

Really!? Someone should tell AMCC tech support then.
When I failed to find a method (other than hooking up
an external GPIO), I contacted them and they came to
the same conclusion (on the 440EP anyway).

I'll look in the latest user manual to be sure ...

PPC440EP_UM2000_v1_23.pdf

p394 has their 'cheesy' implementation of PCI INTA# control;
toggle a single bit.

Then backing up a little, p388 has the PCI command register ...
Nope, no comment there that a write causes an interrupt to
the PowerPC core.

Ok, so going back to the UIC in Chapter 10, p224.

Ah-ha, PCI CMD write generates an interrupt 5!

So, I stand corrected; the host can generate an interrupt to
the PowerPC core, and the method is 'cheesier' than the PCI
INTA# control.

And my experience with AMCC's tech support is now a notch
lower, as even they did not offer this as a solution :)

I sure am glad I changed to a Freescale processor ;)

Cheers,
Dave