PCI target implementation on AMCC PPC CPUs

[David Hawkins]

Hi guys,

> You want to say  PPC440GP cannot be PCI slave without
> this non-transparent bridge because as David said
> its "interrupt pin register hardwired to zero" or
> there other reasons?  I'm trying to use
> PPC440ep(or epx) and from its datasheet I don't
> see anything about this zero hardwiring.
> Does it mean "vanilla" PPC440ep will work?

Look in the user manual p562

https://www.amcc.com/MyAMCC/retrieveDocument/PowerPC/440GP/PPC440GP_UM2002_v1_11.pdf

The processor can generate INTA#.

> I have been finished an application using AMCC
> PPC440GP as PCI target(slave) in the last 2 month.
> I use a non-transparent bridge(AMCC PCI6466) to
> make the device a target(slave) like david has said.

However in this case, the bridge was not required
to make the processor target-capable. Most likely
the board required a local PCI bus, and so the
non-transparent bridge is used to hide the board
PCI devices from the other PCI host.

In this type of design the processor is acting
a *host* on the target board. When a host wants
to interrupt the target, it asserts an interrupt
in the bridge, and that interrupt asserts an
interrupt input on the processor.

When the target processor wants to interrupt the
host it writes to a register in the bridge and
the bridge interrupt the host using its INTA#.

In both cases the bridge is the target and the
processors are both hosts.

:)

Dave