PCI target implementation on AMCC PPC CPUs

[David Hawkins]

Hi Leonid,

> Does somebody have any experience of using AMCC PPC chips (such as
> PPC440ep) or any other PPC at all as PCI target (slave)? PPC440ep has
> PCI-PLB bridge which certainly can be configured as slave. CPU will need
> to do configuration and then I assume another CPU (PCI host) will be
> able to access all memories via the bridge including peripherals'
> controllers. Slave CPU involvement would be minimal then.
> 
> Can anybody point me to design like this or to that end to any SW design
> where PPC CPU works as PCI slave?

I have an application where I want to communicate with up
to 20 cPCI slaves per cPCI chassis, where the slave devices
each use a PowerPC based processor. (The masters happen
to be x86 CPUs; because I have them).

I looked at the 440EP using the Yosemite board

http://www.ovro.caltech.edu/~dwh/powerpc_440ep.pdf

and the Freescale MPC8349E

http://www.ovro.caltech.edu/~dwh/powerpc_mpc8349e.pdf

I had some trouble the with AMCC chips; the DMA controller
operation was weird, and AMCC tech support was pretty
much useless.

Freescale's technical (design) support is great, and they
(the software developers; Kim, Timur, etc) are actively
maintaining/contributing to git trees for u-boot and Linux.
If you can change processors, I'd recommend any Freescale
part over an AMCC part.

I'm working on a cPCI board design at the moment, you're
welcome to look at the design;

  * PowerPC
  * Altera Stratix II FPGAs
  * dual 8-bit 1GHz ADCs

http://www.ovro.caltech.edu/~dwh/carma_board/

Regards,
Dave