[spi-devel-general] [PATCH] Simple driver for Xilinx SPI controler.
Andrei Konovalov
akonovalov at ru.mvista.com
Sun Jun 10 02:58:51 EST 2007
Hi David,
In the bottom there is the interdiff against the previous version of the patch.
The new patch is attached to this message.
Thanks,
Andrei
David Brownell wrote:
> On Wednesday 06 June 2007, Andrei Konovalov wrote:
>> Would be nice to get this driver into mainline.
>> Reviews and comments are welcome.
>
> I'll ignore the Kconfig flamage ... ;)
I've left untouched XILINX_VIRTEX in
+config SPI_XILINX
+ tristate "Xilinx SPI controller"
+ depends on SPI_MASTER && XILINX_VIRTEX && EXPERIMENTAL
as in the current kernel there is no other symbol to "depend on".
If / when someone comes with a separate patch to add XILINX_DRIVERS
or whatever suitable this "depends on" line can be revisited.
>> --- /dev/null
>> +++ b/drivers/spi/xilinx_spi.c
>> @@ -0,0 +1,447 @@
>> +/*
>> + * xilinx_spi.c
>> + *
>> + * Xilinx SPI controler driver (master mode only)
>> + *
>> + * Author: MontaVista Software, Inc.
>> + * source at mvista.com
>> + *
>> + * 2002-2007 (c) MontaVista Software, Inc. This file is licensed under the
>> + * terms of the GNU General Public License version 2. This program is licensed
>> + * "as is" without any warranty of any kind, whether express or implied.
>> + */
>> +
>> +
>> +/* Simple macros to get the code more readable */
>> +#define xspi_in16(addr) in_be16((u16 __iomem *)(addr))
>> +#define xspi_in32(addr) in_be32((u32 __iomem *)(addr))
>> +#define xspi_out16(addr, value) out_be16((u16 __iomem *)(addr), (value))
>> +#define xspi_out32(addr, value) out_be32((u32 __iomem *)(addr), (value))
>
> I'm rather used to seeing I/O addressses passed around as "void __iomem *"
> so those sorts of cast are not needed... :)
The macros has been removed, using "void __iomem *" now.
>> +
>> +static void xspi_abort_transfer(u8 __iomem *regs_base)
>> +{
>
> You should not need an abort primitive. This is called only
> in the remove-controller path. By the time it's called,
> every child spi_device on this bus segment should have been
> removed ... which means any spi_driver attached to that
> device has already returned from its remove() method, which
> in turn means that there will be no spi_message objects in
> flight from any of those drivers.
xspi_abort_transfer() removed
>> +static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
>> +{
>> + struct xilinx_spi *xspi;
>> + u8 __iomem *regs_base;
>> +
>> + xspi = spi_master_get_devdata(spi->master);
>> + regs_base = xspi->regs;
>> +
>> + if (is_on == BITBANG_CS_INACTIVE) {
>> + /* Deselect the slave on the SPI bus */
>> + xspi_out32(regs_base + XSPI_SSR_OFFSET, 0xffff);
>
> I take it you can't support SPI_CS_HIGH??
Yes.
>> +/* spi_bitbang requires custom setup_transfer() to be defined if there is a
>> + * custom txrx_bufs(). We have nothing to setup here as the SPI IP block
>> + * supports just 8 bits per word, and SPI clock can't be changed in software.
>> + * Check for 8 bits per word; speed_hz checking could be added if the SPI
>> + * clock information is available. Chip select delay calculations could be
>> + * added here as soon as bitbang_work() can be made aware of the delay value.
>> + */
>> +static int xilinx_spi_setup_transfer(struct spi_device *spi,
>> + struct spi_transfer *t)
>> +{
>> + u8 bits_per_word;
>> +
>> + bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
>> + if (bits_per_word != 8)
>> + return -EINVAL;
>
> Speed checking *SHOULD* be added; the clock info can be platform data.
Speed checking has be added.
The current problem is that EDK (the tool to create the FPGA "image"
thus configuring what devices are in it) doesn't put the SPI clock
information into any *.c or *.h file it generates. I've tried to
address that in the "enable SPI driver for ML300" patch, but this
doesn't affect the driver patch.
> (Although in practice it's best to have the transfer method do
> the error checking, so that messages that will fail do so before
> they are allowed to enter the I/O queue.)
>
> ISTR you may need to delegate to the default method here too, but
> it's been a while since I poked at that level and the issue might
> not apply to this particular driver config.
As far as I can tell, for the drivers relying on spi_bitbabg
the setup_transfer() method is the right place for the speed
checking.
>> +
>> + return 0;
>> +}
>> +
>> +
>> +static int xilinx_spi_setup(struct spi_device *spi)
>> +{
>> + struct spi_bitbang *bitbang;
>> + struct xilinx_spi *xspi;
>> + int retval;
>> +
>> + xspi = spi_master_get_devdata(spi->master);
>> + bitbang = &xspi->bitbang;
>
> You need to verify ALL the input parameters. In particular,
> mask spi->mode against all the values this driver recognizes
> and supports. If you don't support SPI_LSB_FIRST it's a bug
> if setup() succeeds after setting that. Same thing with all
> other bits defined today (SPI_3WIRE, SPI_CS_HIGH) and in the
> future...
Done
>> + ...
>> +
>> +static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
>> +{
>> + struct xilinx_spi *xspi;
>> + u8 __iomem *regs_base;
>> + u32 ipif_isr;
>> +
>> + xspi = (struct xilinx_spi *) dev_id;
>> + regs_base = xspi->regs;
>> +
>> + /* Get the IPIF inetrrupts, and clear them immediately */
>
> Spell checkers will tell you this is "interrupts" ... ;)
Fixed
>> + ipif_isr = xspi_in32(regs_base + XIPIF_V123B_IISR_OFFSET);
>> + xspi_out32(regs_base + XIPIF_V123B_IISR_OFFSET, ipif_isr);
>> +
>> + if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
>> + u16 cr;
>> + u8 sr;
>> +
>> + /* A transmit has just completed. Process received data and
>> + * check for more data to transmit. Always inhibit the
>> + * transmitter while the Isr refills the transmit register/FIFO,
>> + * or make sure it is stopped if we're done.
>> + */
>> + cr = xspi_in16(regs_base + XSPI_CR_OFFSET);
>> + xspi_out16(regs_base + XSPI_CR_OFFSET,
>> + cr | XSPI_CR_TRANS_INHIBIT);
>> +
>> + /* Read out all the data from the Rx FIFO */
>> + sr = in_8(regs_base + XSPI_SR_OFFSET);
>> + while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
>> + u8 data;
>> +
>> + data = in_8(regs_base + XSPI_RXD_OFFSET);
>> + if (xspi->rx_ptr) {
>> + *xspi->rx_ptr++ = data;
>> + }
>> + sr = in_8(regs_base + XSPI_SR_OFFSET);
>> + }
>> +
>> + /* See if there is more data to send */
>> + if (xspi->remaining_bytes > 0) {
>> + /* sr content is valid here; no need for io_8() */
>> + while ((sr & XSPI_SR_TX_FULL_MASK) == 0
>> + && xspi->remaining_bytes > 0) {
>> + if (xspi->tx_ptr) {
>> + out_8(regs_base + XSPI_TXD_OFFSET,
>> + *xspi->tx_ptr++);
>> + } else {
>> + out_8(regs_base + XSPI_TXD_OFFSET, 0);
>> + }
>
> This duplicates the loop in txrx_bufs(); that's bad style.
> Have one routine holding the shared code.
Moved into separate function.
>> +static int __init xilinx_spi_probe(struct platform_device *dev)
>> +{
>> + int ret = 0;
>> + struct spi_master *master;
>> + struct xilinx_spi *xspi;
>> + struct xspi_platform_data *pdata;
>> + struct resource *r;
>> +
>> + /* Get resources(memory, IRQ) associated with the device */
>> + master = spi_alloc_master(&dev->dev, sizeof(struct xilinx_spi));
>> +
>> + if (master == NULL) {
>> + return -ENOMEM;
>> + }
>> +
>> + platform_set_drvdata(dev, master);
>> + pdata = dev->dev.platform_data;
>> +
>> + if (pdata == NULL) {
>> + ret = -ENODEV;
>> + goto put_master;
>> + }
>> +
>> + r = platform_get_resource(dev, IORESOURCE_MEM, 0);
>> + if (r == NULL) {
>> + ret = -ENODEV;
>> + goto put_master;
>> + }
>> +
>> + xspi = spi_master_get_devdata(master);
>> + xspi->bitbang.master = spi_master_get(master);
>> + xspi->bitbang.chipselect = xilinx_spi_chipselect;
>> + xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
>> + xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
>> + xspi->bitbang.master->setup = xilinx_spi_setup;
>> + init_completion(&xspi->done);
>> +
>> + xspi->regs = ioremap(r->start, r->end - r->start + 1);
>
> Strictly speaking a request_region() should precede the ioremap,
> but a lot of folk don't bother. However, lacking that I'd put
> the request_irq() earlier, since that will be the only resource
> providing any guard against another driver sharing the hardware.
request_region() added
Here is the interdiff against the previous version of the patch:
diff -u b/arch/ppc/syslib/virtex_devices.h b/arch/ppc/syslib/virtex_devices.h
--- b/arch/ppc/syslib/virtex_devices.h
+++ b/arch/ppc/syslib/virtex_devices.h
@@ -49,6 +49,7 @@
struct xspi_platform_data {
s16 bus_num;
u16 num_chipselect;
+ u32 speed_hz;
};
#endif /* __ASM_VIRTEX_DEVICES_H__ */
diff -u b/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
--- b/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -71,12 +71,6 @@
#define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
#define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
-/* Simple macros to get the code more readable */
-#define xspi_in16(addr) in_be16((u16 __iomem *)(addr))
-#define xspi_in32(addr) in_be32((u32 __iomem *)(addr))
-#define xspi_out16(addr, value) out_be16((u16 __iomem *)(addr), (value))
-#define xspi_out32(addr, value) out_be32((u32 __iomem *)(addr), (value))
-
struct xilinx_spi {
/* bitbang has to be first */
struct spi_bitbang bitbang;
@@ -87,62 +81,48 @@
u32 irq;
+ u32 speed_hz; /* SCK has a fixed frequency of speed_hz Hz */
+
u8 *rx_ptr; /* pointer in the Tx buffer */
const u8 *tx_ptr; /* pointer in the Rx buffer */
int remaining_bytes; /* the number of bytes left to transfer */
};
-static void xspi_abort_transfer(u8 __iomem *regs_base)
-{
- /* Deselect the slave on the SPI bus */
- xspi_out32(regs_base + XSPI_SSR_OFFSET, 0xffff);
-
- /* Terminate transmit in progress (if any) and Reset the FIFOs */
- xspi_out16(regs_base + XSPI_CR_OFFSET,
- xspi_in16(regs_base + XSPI_CR_OFFSET)
- | XSPI_CR_TRANS_INHIBIT | XSPI_CR_TXFIFO_RESET
- | XSPI_CR_RXFIFO_RESET);
-}
-
-static void xspi_init_hw(u8 __iomem *regs_base)
+static void xspi_init_hw(void __iomem *regs_base)
{
/* Reset the SPI device */
- xspi_out32(regs_base + XIPIF_V123B_RESETR_OFFSET,
- XIPIF_V123B_RESET_MASK);
+ out_be32(regs_base + XIPIF_V123B_RESETR_OFFSET,
+ XIPIF_V123B_RESET_MASK);
/* Disable all the interrupts just in case */
- xspi_out32(regs_base + XIPIF_V123B_IIER_OFFSET, 0);
+ out_be32(regs_base + XIPIF_V123B_IIER_OFFSET, 0);
/* Enable the global IPIF interrupt */
- xspi_out32(regs_base + XIPIF_V123B_DGIER_OFFSET,
- XIPIF_V123B_GINTR_ENABLE);
+ out_be32(regs_base + XIPIF_V123B_DGIER_OFFSET,
+ XIPIF_V123B_GINTR_ENABLE);
/* Deselect the slave on the SPI bus */
- xspi_out32(regs_base + XSPI_SSR_OFFSET, 0xffff);
+ out_be32(regs_base + XSPI_SSR_OFFSET, 0xffff);
/* Disable the transmitter, enable Manual Slave Select Assertion,
* put SPI controller into master mode, and enable it */
- xspi_out16(regs_base + XSPI_CR_OFFSET,
- XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT
- | XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE);
+ out_be16(regs_base + XSPI_CR_OFFSET,
+ XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT
+ | XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE);
}
static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
{
- struct xilinx_spi *xspi;
- u8 __iomem *regs_base;
-
- xspi = spi_master_get_devdata(spi->master);
- regs_base = xspi->regs;
+ struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
if (is_on == BITBANG_CS_INACTIVE) {
/* Deselect the slave on the SPI bus */
- xspi_out32(regs_base + XSPI_SSR_OFFSET, 0xffff);
+ out_be32(xspi->regs + XSPI_SSR_OFFSET, 0xffff);
} else if (is_on == BITBANG_CS_ACTIVE) {
/* Set the SPI clock phase and polarity */
- u16 cr = xspi_in16(regs_base + XSPI_CR_OFFSET)
+ u16 cr = in_be16(xspi->regs + XSPI_CR_OFFSET)
& ~XSPI_CR_MODE_MASK;
if (spi->mode & SPI_CPHA)
cr |= XSPI_CR_CPHA;
if (spi->mode & SPI_CPOL)
cr |= XSPI_CR_CPOL;
- xspi_out16(regs_base + XSPI_CR_OFFSET, cr);
+ out_be16(xspi->regs + XSPI_CR_OFFSET, cr);
/* We do not check spi->max_speed_hz here as the SPI clock
* frequency is not software programmable (the IP block design
@@ -150,30 +130,43 @@
*/
/* Activate the chip select */
- xspi_out32(regs_base + XSPI_SSR_OFFSET,
- ~(0x0001 << spi->chip_select));
+ out_be32(xspi->regs + XSPI_SSR_OFFSET,
+ ~(0x0001 << spi->chip_select));
}
}
/* spi_bitbang requires custom setup_transfer() to be defined if there is a
* custom txrx_bufs(). We have nothing to setup here as the SPI IP block
* supports just 8 bits per word, and SPI clock can't be changed in software.
- * Check for 8 bits per word; speed_hz checking could be added if the SPI
- * clock information is available. Chip select delay calculations could be
+ * Check for 8 bits per word. Chip select delay calculations could be
* added here as soon as bitbang_work() can be made aware of the delay value.
*/
static int xilinx_spi_setup_transfer(struct spi_device *spi,
struct spi_transfer *t)
{
u8 bits_per_word;
+ u32 hz;
+ struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
- if (bits_per_word != 8)
+ hz = (t) ? t->speed_hz : spi->max_speed_hz;
+ if (bits_per_word != 8) {
+ dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
+ __FUNCTION__, bits_per_word);
return -EINVAL;
+ }
+
+ if (hz && xspi->speed_hz > hz) {
+ dev_err(&spi->dev, "%s, unsupported clock rate %uHz\n",
+ __FUNCTION__, hz);
+ return -EINVAL;
+ }
return 0;
}
+/* the spi->mode bits understood by this driver: */
+#define MODEBITS (SPI_CPOL | SPI_CPHA)
static int xilinx_spi_setup(struct spi_device *spi)
{
@@ -186,63 +179,70 @@
if (!spi->bits_per_word)
spi->bits_per_word = 8;
+
+ if (spi->mode & ~MODEBITS) {
+ dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
+ __FUNCTION__, spi->mode & ~MODEBITS);
+ return -EINVAL;
+ }
retval = xilinx_spi_setup_transfer(spi, NULL);
if (retval < 0)
return retval;
dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
- __FUNCTION__, spi->mode & (SPI_CPOL | SPI_CPHA),
- spi->bits_per_word, 0);
+ __FUNCTION__, spi->mode & MODEBITS, spi->bits_per_word, 0);
return 0;
}
+static inline void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
+{
+ u8 sr;
+
+ /* Fill the Tx FIFO with as many bytes as possible */
+ sr = in_8(xspi->regs + XSPI_SR_OFFSET);
+ while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
+ if (xspi->tx_ptr) {
+ out_8(xspi->regs + XSPI_TXD_OFFSET, *xspi->tx_ptr++);
+ } else {
+ out_8(xspi->regs + XSPI_TXD_OFFSET, 0);
+ }
+ xspi->remaining_bytes--;
+ sr = in_8(xspi->regs + XSPI_SR_OFFSET);
+ }
+}
+
static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
{
- struct xilinx_spi *xspi;
- u8 __iomem *regs_base;
+ struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
u32 ipif_ier;
u16 cr;
- u8 sr;
/* We get here with transmitter inhibited */
- xspi = spi_master_get_devdata(spi->master);
- regs_base = xspi->regs;
-
xspi->tx_ptr = t->tx_buf;
xspi->rx_ptr = t->rx_buf;
xspi->remaining_bytes = t->len;
INIT_COMPLETION(xspi->done);
- /* Fill the Tx FIFO with as many bytes as possible */
- sr = in_8(regs_base + XSPI_SR_OFFSET);
- while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
- if (xspi->tx_ptr) {
- out_8(regs_base + XSPI_TXD_OFFSET, *xspi->tx_ptr++);
- } else {
- out_8(regs_base + XSPI_TXD_OFFSET, 0);
- }
- xspi->remaining_bytes--;
- sr = in_8(regs_base + XSPI_SR_OFFSET);
- }
+ xilinx_spi_fill_tx_fifo(xspi);
/* Enable the transmit empty interrupt, which we use to determine
* progress on the transmission.
*/
- ipif_ier = xspi_in32(regs_base + XIPIF_V123B_IIER_OFFSET);
- xspi_out32(regs_base + XIPIF_V123B_IIER_OFFSET,
- ipif_ier | XSPI_INTR_TX_EMPTY);
+ ipif_ier = in_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET);
+ out_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET,
+ ipif_ier | XSPI_INTR_TX_EMPTY);
/* Start the transfer by not inhibiting the transmitter any longer */
- cr = xspi_in16(regs_base + XSPI_CR_OFFSET) & ~XSPI_CR_TRANS_INHIBIT;
- xspi_out16(regs_base + XSPI_CR_OFFSET, cr);
+ cr = in_be16(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_TRANS_INHIBIT;
+ out_be16(xspi->regs + XSPI_CR_OFFSET, cr);
wait_for_completion(&xspi->done);
/* Disable the transmit empty interrupt */
- xspi_out32(regs_base + XIPIF_V123B_IIER_OFFSET, ipif_ier);
+ out_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET, ipif_ier);
return t->len - xspi->remaining_bytes;
}
@@ -255,16 +255,12 @@
*/
static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
{
- struct xilinx_spi *xspi;
- u8 __iomem *regs_base;
+ struct xilinx_spi *xspi = dev_id;
u32 ipif_isr;
- xspi = (struct xilinx_spi *) dev_id;
- regs_base = xspi->regs;
-
- /* Get the IPIF inetrrupts, and clear them immediately */
- ipif_isr = xspi_in32(regs_base + XIPIF_V123B_IISR_OFFSET);
- xspi_out32(regs_base + XIPIF_V123B_IISR_OFFSET, ipif_isr);
+ /* Get the IPIF interrupts, and clear them immediately */
+ ipif_isr = in_be32(xspi->regs + XIPIF_V123B_IISR_OFFSET);
+ out_be32(xspi->regs + XIPIF_V123B_IISR_OFFSET, ipif_isr);
if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
u16 cr;
@@ -275,40 +271,29 @@
* transmitter while the Isr refills the transmit register/FIFO,
* or make sure it is stopped if we're done.
*/
- cr = xspi_in16(regs_base + XSPI_CR_OFFSET);
- xspi_out16(regs_base + XSPI_CR_OFFSET,
- cr | XSPI_CR_TRANS_INHIBIT);
+ cr = in_be16(xspi->regs + XSPI_CR_OFFSET);
+ out_be16(xspi->regs + XSPI_CR_OFFSET,
+ cr | XSPI_CR_TRANS_INHIBIT);
/* Read out all the data from the Rx FIFO */
- sr = in_8(regs_base + XSPI_SR_OFFSET);
+ sr = in_8(xspi->regs + XSPI_SR_OFFSET);
while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
u8 data;
- data = in_8(regs_base + XSPI_RXD_OFFSET);
+ data = in_8(xspi->regs + XSPI_RXD_OFFSET);
if (xspi->rx_ptr) {
*xspi->rx_ptr++ = data;
}
- sr = in_8(regs_base + XSPI_SR_OFFSET);
+ sr = in_8(xspi->regs + XSPI_SR_OFFSET);
}
/* See if there is more data to send */
if (xspi->remaining_bytes > 0) {
- /* sr content is valid here; no need for io_8() */
- while ((sr & XSPI_SR_TX_FULL_MASK) == 0
- && xspi->remaining_bytes > 0) {
- if (xspi->tx_ptr) {
- out_8(regs_base + XSPI_TXD_OFFSET,
- *xspi->tx_ptr++);
- } else {
- out_8(regs_base + XSPI_TXD_OFFSET, 0);
- }
- xspi->remaining_bytes--;
- sr = in_8(regs_base + XSPI_SR_OFFSET);
- }
+ xilinx_spi_fill_tx_fifo(xspi);
/* Start the transfer by not inhibiting the
* transmitter any longer
*/
- xspi_out16(regs_base + XSPI_CR_OFFSET, cr);
+ out_be16(xspi->regs + XSPI_CR_OFFSET, cr);
} else {
/* No more data to send.
* Indicate the transfer is completed.
@@ -359,6 +344,12 @@
xspi->bitbang.master->setup = xilinx_spi_setup;
init_completion(&xspi->done);
+ if (!request_mem_region(r->start,
+ r->end - r->start + 1, XILINX_SPI_NAME)) {
+ ret = -ENXIO;
+ goto put_master;
+ }
+
xspi->regs = ioremap(r->start, r->end - r->start + 1);
if (xspi->regs == NULL) {
ret = -ENOMEM;
@@ -373,6 +364,7 @@
master->bus_num = pdata->bus_num;
master->num_chipselect = pdata->num_chipselect;
+ xspi->speed_hz = pdata->speed_hz;
/* SPI controller initializations */
xspi_init_hw(xspi->regs);
@@ -411,7 +403,6 @@
xspi = spi_master_get_devdata(master);
spi_bitbang_stop(&xspi->bitbang);
- xspi_abort_transfer(xspi->regs);
free_irq(xspi->irq, xspi);
iounmap(xspi->regs);
platform_set_drvdata(dev, 0);
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