General fx60 notes, Question regarding forcing EDK to locate program code at an address

Wade Maxfield wmaxfield at
Fri Jan 19 09:16:38 EST 2007

  We are working on debugging an FX60 load.  We appear to have something
going into our DDR ram from the compact flash.

   We have learned some things about the fx60 I'd like to share without
giving away secrets.

  It turns out that the FX60 JTAG controller should be hooked up to PPC_1 as
the primary power pc in the chip.

   We found the 8.1 command line impact almost never runs right, so we use
7.1 impact to generate our system ace file.

   Our .opt file looks like the following.  Note that you MUST identify each
device on the jtag chain (minus the system.ace) in order for the
system.aceto do its magic Load the Xilinx trick.  If you don't tell it
of all the
devices on the chain, it will error out, even if those devices are cpld's
and there is not any xilinx load for them in the system.ace file.


-ace system.ace
-hw implementation/download.bit
-board user
-target ppc_hw
-configdevice devicenr 1 idcode 0x21eb4093 irlength 14 partname xc4vfx60
-configdevice devicenr 2 idcode 0x16d8a093 irlength 8 partname xc2c128
-debugdevice devicenr 1 cpunr 2
-elf linux/zImage.elf
-elf ppc405_0/code/memtest.elf

our command line is as follows
xmd -tcl genace.tcl  -opt genace.opt

The debug device appears to affect which cpu gets the PC reset location
after the .elf file is located.

 The memtest.elf file is stuck in the ppc405_0 directory because that is
where it started, and the gui won't let us change it without rebuilding the
 We are loading two .elf files so that we have the program counter set to
the internal (Block Ram) memory test/boot loader after the .elf files are
finished loading.  This lets us look at our ddr ram memory and prove the
linux load made it there.  The first .elf file loads, then the second one,
then the pc is set to the start address of the second .elf file.  Since the
second .elf file loads into block ram, it is doing nothing, as that is
determined by the bitstream in the fpga fabric.  There may be easier ways to
do this.


  What I would like to do is create a .elf file with the Xilinx EDK and
force it to be located at a particular address (0x400000 for example).
  I've looked and looked, but obviously I've not looked at the right
  Does anyone know how to do this with the Xilinx EDK?

We'll be using this to prove that we can or cannot execute out of DDR ram.
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