8360E - PCI / DTC Blob Setup

[Russell McGuire]

This might be the wrong forum to discuss HW routing, but I am not sure of
many HW guys that would understand blob setups. I know I still don't.

I read through the booting-without-of-tree.txt and it doesn't explain this
other than the interrupt routing needs to be present. Perhaps some of the
maintainers of the 83xx platforms can explain how this blob is developed?
I assume their board work with the submitted mp38360emds.dts files, as an
example.

Let me see if I can simplify this, I had this schematic reviewed by Pericom
<a PCI bridge MFG> and they recommended these IDSEL lines. And I know the
card detection works great, in U-boot.

My external PCI bridge is the only thing routed directly to the 8360 Host
bridge. The PCI Host bridge in my system is connected on IDSEL->AD25,0x19
Perhaps I shouldn't use any interrupt routing for this, as there is no true
/INTA line tied directly to the bridge?

My Three PCI slots are routed as follows:

Bus 0, Bridge Chip, IDSEL = AD25

Other side of the Host bridge, all are routed to INTA directly to the 
CPU.
Bus 1, Slot 1, IDSEL = AD20 <card would be ID'd as 1.04 (Bus.Dev)>
Bus 1, Slot 2, IDSEL = AD24 <card would be ID'd as 1.08 (Bus.Dev)>
Bus 2, Slot 1, IDSEL = AD20 <card would be ID'd as 2.04 (Bus.Dev)>

That being said:
/* IDSEL 0x19 AD25*/
 c800 0 0 1 700 14 8

I see in the c800 directly corresponds to the 83xx manual for PCI CONFIG
address mapping for AD25.

I think the '1' is mapped to /INTA, which is the only PCI INT available in
the 8360E.

I understand the 700 in this case is the address of the PIC at 700.

That leaves 5 fields/questions.
1) What do the first two '0's after c800 mean?
2) What does the '14' map to?
3) What does the '8' map to?
4) Why would some boards map multiple interrupts to a single IDSEL, like the
mpc8360emds.dts file? Is this to handle extra bridges that might be plugged
in at a later time?

If I understand the mapping correctly then I think I can hard code in the
interrupts for the PCI slots.

So I don't drive everybody nuts, is there actual documentation on this. I
would be happy to stop spamming this list... :-)

-Russ
-----Original Message-----
From: Kumar Gala [mailto:galak at kernel.crashing.org] 
Sent: Thursday, February 01, 2007 6:33 AM
To: rmcguire at videopresence.com
Cc: linuxppc-embedded at ozlabs.org
Subject: Re: 8360E - PCI / DTC Blob Setup


On Feb 1, 2007, at 8:27 AM, Russell McGuire wrote:

> Since I am hip deep in debugging the PCI system.
>
> In the .dts files there is the section for the PCI setup.
>
> The interrupt-map = < >
>
> Does this need to include:
> 1) A mapping for every IDSEL line in the system?
> 2) Only those IDSELs that are used on the slots on the motherboard?

I'm not sure I follow the difference between 1/2. The map needs to  
cover every IDSEL that has an IRQ line wired to it.

> 3) A custom entry for every card we want to support?

See above.

> 4) How does a bridge chip and slave busses affect the entries, if  
> at all?

Uugh, I'm not sure how bridges are handled at this point.

> Looking at the mpc8360 / 8349 setups that are part of the latest  
> kernel
> trees, some are place many and some are placing just a single entry?
>
> Which should be the preferred method?

It depends on your HW setup, the 8360/49 boards have some 'odd' IDSEL  
irq mapping.

- k