Kernel 2.6.23 on ML-403 hangs with uncompression on bootup

Thu Dec 13 03:10:40 EST 2007

Hi All,

I m using Linux 2.6.23-rc2 from Grant's git with gcc 4.1.0 on ML-403. When I
load the zImage from the XMD, I only get the messages printed from the
arch/ppc/boot and soon after the kernel is decompressed the console appears
frozen. So I assume the console is ok with image loader but on linux kernel,
it doesnt seem working. I edited the code in arch/ppc/boot/simple so as to
forcefully refer the right embed_config() function.

Following is the console logs,
loaded at:     00400000 004D71A0
board data at: 004D5124 004D51A0
relocated to:  00404048 004040C4
zimage at:     00404F11 004D4DFC
avail ram:     004D8000 02000000
Linux/PPC load: console=ttyS0,9600
Uncompressing Linux...done.
Now booting the kernel
com_port is 40401003
id mach(): done
MMU:enter
MMU:hw init
MMU:mapin
MMU:setio
MMU:exit

When I dumped the __log_buffer, I only find the linux_banner being
displayed, the others remain zero. Periodically I stopped the ppc to find
the PC using XMD. Eachtime I stopped it was different either with address
0xCxxx_xxxx or 0x0xxx_xxxx. So I suspect this could be a console problem as
kernel appears running.
It would be helpful if someone could let me know, whether anything
more needs to be done to bring the console. In xparameters_ml403.h the PLB
speed is 100000000 and I havent edited any other file. Also, I have
configured the command line parameters to kernel as
CONFIG_CMDLINE="console=ttyS0,9600".
Whether there are any conflicts between the compiler being used and linux
version despite the changes to correctly refer the embed_config(). Also,
please let me know whether printk keeps dumping on __log_buffer even after
the console is initialized and are there anyway to keep printk dumping to
__log_buffer irrespective of the console being initialzed or not.
Any suggestions and ideas would be very helpful.

Thanks and Regards,
Ram

PS: Attached is config file and below is xparameters file

xparameters_ml403.h
------------------------------------------------------
/* Definitions for driver UARTNS550 */
#define XPAR_XUARTNS550_NUM_INSTANCES 1
#define XPAR_XUARTNS550_CLOCK_HZ 100000000
/* Definitions for peripheral RS232_UART */
#define XPAR_RS232_UART_BASEADDR 0x40400000
#define XPAR_RS232_UART_HIGHADDR 0x4040FFFF
#define XPAR_RS232_UART_DEVICE_ID 0

/******************************************************************/
/* Definitions for driver IIC */
#define XPAR_XIIC_NUM_INSTANCES 1
/* Definitions for peripheral IIC_EEPROM */
#define XPAR_IIC_EEPROM_BASEADDR 0x40800000
#define XPAR_IIC_EEPROM_HIGHADDR 0x4080FFFF
#define XPAR_IIC_EEPROM_DEVICE_ID 0
#define XPAR_IIC_EEPROM_TEN_BIT_ADR 0
#define XPAR_IIC_EEPROM_GPO_WIDTH 1

/******************************************************************/
#define XPAR_XSYSACE_MEM_WIDTH 16
/* Definitions for driver SYSACE */
#define XPAR_XSYSACE_NUM_INSTANCES 1
/* Definitions for peripheral SYSACE_COMPACTFLASH */
#define XPAR_SYSACE_COMPACTFLASH_BASEADDR 0x41800000
#define XPAR_SYSACE_COMPACTFLASH_HIGHADDR 0x4180FFFF
#define XPAR_SYSACE_COMPACTFLASH_DEVICE_ID 0
#define XPAR_SYSACE_COMPACTFLASH_MEM_WIDTH 16

/******************************************************************/

/* Definitions for peripheral SRAM_256KX32 */
#define XPAR_SRAM_256KX32_NUM_BANKS_MEM 1

/******************************************************************/
/* Definitions for peripheral SRAM_256KX32 */
#define XPAR_SRAM_256KX32_MEM0_BASEADDR 0x40500000
#define XPAR_SRAM_256KX32_MEM0_HIGHADDR 0x405FFFFF
/******************************************************************/
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 4
#define XPAR_XINTC_HAS_IPR 1
#define XPAR_XINTC_USE_DCR 0
/* Definitions for driver INTC */
#define XPAR_XINTC_NUM_INSTANCES 1
/* Definitions for peripheral OPB_INTC_0 */
#define XPAR_OPB_INTC_0_BASEADDR 0x41200000
#define XPAR_OPB_INTC_0_HIGHADDR 0x4120FFFF
#define XPAR_OPB_INTC_0_DEVICE_ID 0
#define XPAR_OPB_INTC_0_KIND_OF_INTR 0x00000000

/******************************************************************/
#define XPAR_INTC_SINGLE_BASEADDR 0x41200000
#define XPAR_INTC_SINGLE_HIGHADDR 0x4120FFFF
#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
#define XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK 0X000001
#define XPAR_OPB_INTC_0_ETHERNET_MAC_IP2INTC_IRPT_INTR 0
#define XPAR_SYSACE_COMPACTFLASH_SYSACE_IRQ_MASK 0X000002
#define XPAR_OPB_INTC_0_SYSACE_COMPACTFLASH_SYSACE_IRQ_INTR 1
#define XPAR_IIC_EEPROM_IP2INTC_IRPT_MASK 0X000004
#define XPAR_OPB_INTC_0_IIC_EEPROM_IP2INTC_IRPT_INTR 2
#define XPAR_RS232_UART_IP2INTC_IRPT_MASK 0X000008
#define XPAR_OPB_INTC_0_RS232_UART_IP2INTC_IRPT_INTR 3
/******************************************************************/
/* Definitions for driver DDR */
#define XPAR_XDDR_NUM_INSTANCES 1
/* Definitions for peripheral DDR_SDRAM_64MX32 */
#define XPAR_DDR_SDRAM_64MX32_ECC_BASEADDR 0xFFFFFFFF
#define XPAR_DDR_SDRAM_64MX32_ECC_HIGHADDR 0x00000000
#define XPAR_DDR_SDRAM_64MX32_DEVICE_ID 0
#define XPAR_DDR_SDRAM_64MX32_INCLUDE_ECC_INTR 0

/******************************************************************/
/* Definitions for peripheral DDR_SDRAM_64MX32 */
#define XPAR_DDR_SDRAM_64MX32_MEM0_BASEADDR 0x00000000
#define XPAR_DDR_SDRAM_64MX32_MEM0_HIGHADDR 0x03FFFFFF
/******************************************************************/
/* Definitions for driver EMAC */
#define XPAR_XEMAC_NUM_INSTANCES 1
/* Definitions for peripheral ETHERNET_MAC */
#define XPAR_ETHERNET_MAC_BASEADDR 0x80400000
#define XPAR_ETHERNET_MAC_HIGHADDR 0x8040FFFF
#define XPAR_ETHERNET_MAC_DEVICE_ID 0
#define XPAR_ETHERNET_MAC_ERR_COUNT_EXIST 1
#define XPAR_ETHERNET_MAC_DMA_PRESENT 1
#define XPAR_ETHERNET_MAC_MII_EXIST 1
/* Edited by Ramkumar. Dont know whether this will be working.
 */
#define XPAR_ETHERNET_MAC_CAM_EXIST 0
#define XPAR_ETHERNET_MAC_JUMBO_EXIST 0
#define XPAR_ETHERNET_MAC_TX_DRE_TYPE 0
#define XPAR_ETHERNET_MAC_RX_DRE_TYPE 0
#define XPAR_ETHERNET_MAC_TX_INCLUDE_CSUM 0
#define XPAR_ETHERNET_MAC_RX_INCLUDE_CSUM 0

/******************************************************************/

/* Definitions for peripheral PLB_BRAM_IF_CNTLR_1 */
#define XPAR_PLB_BRAM_IF_CNTLR_1_BASEADDR 0xffff0000
#define XPAR_PLB_BRAM_IF_CNTLR_1_HIGHADDR 0xffffffff

/******************************************************************/
#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 100000000
/******************************************************************/
#define XPAR_CPU_ID 0
#define XPAR_PPC405_VIRTEX4_ID 0
#define XPAR_PPC405_VIRTEX4_CORE_CLOCK_FREQ_HZ 100000000
#define XPAR_PPC405_VIRTEX4_IDCR_BASEADDR 0x00000100
#define XPAR_PPC405_VIRTEX4_IDCR_HIGHADDR 0x0000010F
#define XPAR_PPC405_VIRTEX4_DISABLE_OPERAND_FORWARDING 1
#define XPAR_PPC405_VIRTEX4_MMU_ENABLE 1
#define XPAR_PPC405_VIRTEX4_DETERMINISTIC_MULT 0
#define XPAR_PPC405_VIRTEX4_PLBSYNCBYPASS 1
#define XPAR_PPC405_VIRTEX4_APU_CONTROL 0b1101111000000000
#define XPAR_PPC405_VIRTEX4_APU_UDI_1 0b101000011000100110000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_2 0b101000111000100110000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_3 0b101001011000100111000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_4 0b101001111000100111000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_5 0b101010011000110000000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_6 0b101010111000110000000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_7 0b101011011000110001000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_8 0b101011111000110001000011
#define XPAR_PPC405_VIRTEX4_PVR_HIGH 0b0000
#define XPAR_PPC405_VIRTEX4_PVR_LOW 0b0000
#define XPAR_PPC405_VIRTEX4_HW_VER "1.01.a"
/******************************************************************/

/******************************************************************/
/* Linux Redefines */
/******************************************************************/
#define XPAR_UARTNS550_0_BASEADDR (XPAR_RS232_UART_BASEADDR+0x1000)
#define XPAR_UARTNS550_0_HIGHADDR XPAR_RS232_UART_HIGHADDR
#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
#define XPAR_UARTNS550_0_DEVICE_ID XPAR_RS232_UART_DEVICE_ID
/******************************************************************/
#define XPAR_IIC_0_BASEADDR XPAR_IIC_EEPROM_BASEADDR
#define XPAR_IIC_0_HIGHADDR XPAR_IIC_EEPROM_HIGHADDR
#define XPAR_IIC_0_TEN_BIT_ADR XPAR_IIC_EEPROM_TEN_BIT_ADR
#define XPAR_IIC_0_DEVICE_ID XPAR_IIC_EEPROM_DEVICE_ID
/******************************************************************/
#define XPAR_SYSACE_0_BASEADDR XPAR_SYSACE_COMPACTFLASH_BASEADDR
#define XPAR_SYSACE_0_HIGHADDR XPAR_SYSACE_COMPACTFLASH_HIGHADDR
#define XPAR_SYSACE_0_DEVICE_ID XPAR_SYSACE_COMPACTFLASH_DEVICE_ID
/******************************************************************/
#define XPAR_EMAC_0_BASEADDR XPAR_ETHERNET_MAC_BASEADDR
#define XPAR_EMAC_0_HIGHADDR XPAR_ETHERNET_MAC_HIGHADDR
#define XPAR_EMAC_0_DMA_PRESENT XPAR_ETHERNET_MAC_DMA_PRESENT
#define XPAR_EMAC_0_MII_EXIST XPAR_ETHERNET_MAC_MII_EXIST
#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_ETHERNET_MAC_ERR_COUNT_EXIST
#define XPAR_EMAC_0_CAM_EXIST XPAR_ETHERNET_MAC_CAM_EXIST
#define XPAR_EMAC_0_JUMBO_EXIST XPAR_ETHERNET_MAC_JUMBO_EXIST
#define XPAR_EMAC_0_TX_DRE_TYPE XPAR_ETHERNET_MAC_TX_DRE_TYPE
#define XPAR_EMAC_0_RX_DRE_TYPE XPAR_ETHERNET_MAC_RX_DRE_TYPE
#define XPAR_EMAC_0_TX_INCLUDE_CSUM XPAR_ETHERNET_MAC_TX_INCLUDE_CSUM
#define XPAR_EMAC_0_RX_INCLUDE_CSUM XPAR_ETHERNET_MAC_RX_INCLUDE_CSUM
#define XPAR_EMAC_0_DEVICE_ID XPAR_ETHERNET_MAC_DEVICE_ID
/******************************************************************/
#define XPAR_INTC_0_BASEADDR XPAR_OPB_INTC_0_BASEADDR
#define XPAR_INTC_0_HIGHADDR XPAR_OPB_INTC_0_HIGHADDR
#define XPAR_INTC_0_KIND_OF_INTR XPAR_OPB_INTC_0_KIND_OF_INTR
#define XPAR_INTC_0_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
/******************************************************************/
#define XPAR_INTC_0_EMAC_0_VEC_ID
XPAR_OPB_INTC_0_ETHERNET_MAC_IP2INTC_IRPT_INTR
#define XPAR_INTC_0_SYSACE_0_VEC_ID
XPAR_OPB_INTC_0_SYSACE_COMPACTFLASH_SYSACE_IRQ_INTR
#define XPAR_INTC_0_IIC_0_VEC_ID
XPAR_OPB_INTC_0_IIC_EEPROM_IP2INTC_IRPT_INTR
#define XPAR_INTC_0_UARTNS550_0_VEC_ID
XPAR_OPB_INTC_0_RS232_UART_IP2INTC_IRPT_INTR
/******************************************************************/
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ
#define XPAR_DDR_0_SIZE 33554432
/******************************************************************/
#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400
#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF
#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0
/******************************************************************/
#define XPAR_PCI_0_CLOCK_FREQ_HZ    0
/******************************************************************/
#define XPAR_XPS2_NUM_INSTANCES     2
#define XPAR_PS2_0_DEVICE_ID        50
#define XPAR_PS2_0_BASEADDR         0xA9000000
#define XPAR_PS2_0_HIGHADDR         0xA900003F
#define XPAR_INTC_0_PS2_0_VEC_ID    27
#define XPAR_PS2_1_DEVICE_ID        51
#define XPAR_PS2_1_BASEADDR         0xA9001000
#define XPAR_INTC_0_PS2_1_VEC_ID    26
/******************************************************************/
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