Problems with DMA from user space on MPC834x (Cache coherency?)

[Liu Dave-r63238]

You can make use of the hardware cache coherency. Setup the DMA
attribute as global.
If you use the hardware way, you don't need these flushing operation.

-Dave

> > I added following before starting DMA:
> >
> > kaddr = (unsigned long)kmap(pages[i]); 
> flush_dcache_range(kaddr, kaddr 
> > + PAGE_SIZE); kunmap(pages[i]);
> >
> > ...and everything works now. As I understand this now, 
> dma_map_page is 
> > not flushing caches on MPS834x because the processor should 
> snoop the 
> > memory transactions and flush cache automatically if needed 
> > (__dma_sync_page is defined as do { } while (0) in kernel). 
> But there 
> > exists an errata
> > (PCI5) which states that there may be some problems with this 
> > automatic flushing. So the caches must be flushed with 
> > flush_dcache_range.
> 
> What silicon version are you using.  PCI5 should be fixed in 
> rev1.1 and newer.  You can be taking a big perf hit having to 
> flush all the time.
> 
> - k