[PATCH] Xilinx UART Lite 2.6.18 driver

[Peter Korsgaard]

>>>>> "David" == David Bolcsfoldi <dbolcsfoldi at gmail.com> writes:

David> Here's an initial patch based on a modified uartlite (by Peter
David> Korsgaard), it's by no means ment to be final and any feedback
David> would be appreciated.

Could you make it relative to my driver so the changes are easier to
see?

David> - readb/writeb to in_be32/out_be32.

David> For some reason on my board the readb and writeb don't behave
David> correctly when reading and writing to the uartlite device. I
David> haven't looked into it but if this is unacceptable I will try
David> to revert to readb/writeb.

The PPC is big endian - Did you remember to add 3 to your base
address?

-- 
Bye, Peter Korsgaard