440SP External Interrupt IRQ

[Jeff Stevens]

I'm sorry if this is an easy question, but how do my
schematics tell me that pint IRQ0 uses IRQ 48 in my
board specific PCI IRQ lookup table, where it is
matching up the idsel lines to an irq number?  For
instance, in arch/ppc/platforms/4xx/luan.c it maps PCI
interrupts like:

static inline int
luan_map_irq(struct pci_dev *dev, unsigned char idsel,
unsigned char pin)
{
	struct pci_controller *hose =
pci_bus_to_hose(dev->bus->number);

	/* PCIX0 in adapter mode, no host interrupt routing
*/

	/* PCIX1 */
	if (hose->index == 0) {
		static char pci_irq_table[][4] =
		/*
		 *	PCI IDSEL/INTPIN->INTLINE
		 *	  A   B   C   D
		 */
		{
			{ 49, 49, 49, 49 },	/* IDSEL 1 - PCIX1 Slot 0 */
			{ 49, 49, 49, 49 },	/* IDSEL 2 - PCIX1 Slot 1 */
			{ 49, 49, 49, 49 },	/* IDSEL 3 - PCIX1 Slot 2 */
			{ 49, 49, 49, 49 },	/* IDSEL 4 - PCIX1 Slot 3 */
		};
		const long min_idsel = 1, max_idsel = 4,
irqs_per_slot = 4;
		return PCI_IRQ_TABLE_LOOKUP;
	/* PCIX2 */
	} else if (hose->index == 1) {
		static char pci_irq_table[][4] =
		/*
		 *	PCI IDSEL/INTPIN->INTLINE
		 *	  A   B   C   D
		 */
		{
			{ 50, 50, 50, 50 },	/* IDSEL 1 - PCIX2 Slot 0 */
			{ 50, 50, 50, 50 },	/* IDSEL 2 - PCIX2 Slot 1 */
			{ 50, 50, 50, 50 },	/* IDSEL 3 - PCIX2 Slot 2 */
			{ 50, 50, 50, 50 },	/* IDSEL 4 - PCIX2 Slot 3 */
		};
		const long min_idsel = 1, max_idsel = 4,
irqs_per_slot = 4;
		return PCI_IRQ_TABLE_LOOKUP;
	}
	return -1;
}

Based on their schematics, I assume:
IRQ Line      IRQ#
  IRQ0        48
  IRQ1        49
  IRQ2        50
  IRQ3        51
  IRQ4        52
  IRQ5        53

I just hate assuming, and would like to understand how
they come up with the IRQ offset for the external
interrups.

-Jeff

--- Stefan Roese <sr at denx.de> wrote:

> Jeff,
> 
> On Friday 06 October 2006 05:49, Jeff Stevens wrote:
> > I am trying to figure out the PCI IRQ mapping on a
> > 440SP processor in linux-2.6.17.9.  I have a board
> > that is based off of the Luan development board,
> and I
> > am not sure which IRQ corresponds to each external
> > IRQ[0:5] pins on the processor.  Where can I find
> this
> > information?
> 
> In your schematics. Sorry but it's that simple.
> 
> Best regards,
> Stefan
> 


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