Processor reset and cache inhibit

[Sachin Rane]

Hi,

 

While reading PPC440 processor's User Manual, I came across following
lines:

"After processor reset, hardware automatically sets the caching
inhibited storage attribute for the memory

page containing the reset address, and also automatically flash
invalidates the instruction cache."

 

Could you explain me why it is necessary to set the caching inhibit
storage attribute of the memory page containing the reset address?

 

Thanks and Regards,

Sachin Rane

-------------- next part --------------
An HTML attachment was scrubbed...
URL: http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20061115/24d87bd3/attachment.htm