Memory mapping PCI memory region to user space

[David Hawkins]

Hi Mark,

> Ok, I should be a little more specific.

Ok :)

> Yes, I/O space is little endian, and any configuration
> registers and such are little endian.  But memory space
> is strictly 32 bit as far as PCI is concerned.
> (forgetting 64 bit PCI for the moment) The two lower
> bits of address are not used, and there is no required 
> correlation of byte enables to those missing address bits.
> 
> So, the point is, Freescale swaps bytes between its internal
> bus and PCI.  Other processors (like TI DSPs) do not.  I
> don't know that one method is necessarily right, but the fact
> that we have this discussion periodically suggests that Freescale's 
> method is not the best.

Hmm, I'd have to look on the PCI bus with the analyzer to
confirm this ... but I do recall seeing a mapping of
the 128-bit PLB to PCI bus in the 440EP manual, so
you're probably right.

The PLX PCI-9054 has an 'endianness' option like this too.
I believe its so you can use a PPC on the local bus, and
swap bytes when the are written onto the PCI bus.
Sounds like the Freescale SoC bridges have just hardcoded
that type of implementation.

> This might be an academic point, but I think it does help to
> see the distinction.  To talk to a device over PCI you must
> know how both ends map their internal buss(es) to PCI,
> and it's not directly a big/little endian issue.

Its nice to be aware of these subtle differences.

Thanks for the discussion.

Dave