caches on Virtex 4

Martin, Tim tim.martin at
Thu Jul 27 07:18:53 EST 2006


There are several registers/etc that affect the caches on the Virtex4
PPC core.

Step 1 - Make sure your FPGA is configured to have caches in the memory
regions you're interested in caching.  Your FPGA designer should have
done this in the EDK (check options in the MHS file).

Step 2 - Make sure the individual cache regions are enabled.  Look at
the Xilinx standalone BSP to see how this works, or read the processor
manual.  E.g. xcache_l.c (a Xilinx standalone BSP file) in
XCache_EnableDCache modifies SGR, DCWR, and DCCR SPRs.
Xcache_EnableICache modifies SGR and ICCR SPRs.

Step 3- Make sure the cache configuration register (CCR0) is configured

By default, I'm pretty sure you only need to worry about Step 1, as I
thought Step2 and 3 were handled by the kernel early in the boot process
and/or u-boot.

> -----Original Message-----
> From: at 
> [ at ozlabs.or
> g] On Behalf Of heiguga
> Sent: Wednesday, July 26, 2006 10:59 AM
> To: linuxppc-embedded at
> Subject: caches on Virtex 4
> Hi!
> I am working on an ml403 board (virtex4 with ppc core). I am 
> sucessfully using Linux 2.4 and 2.6.
> I have done a few performance tests with networking, applications...
> How can i ensure, that the caches are turned on? (is there a special
> Register?)
> Where are the caches turned on?
> nice greetings
> Robert
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> Linuxppc-embedded mailing list
> Linuxppc-embedded at

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