440gx GPIO

[Howard, Marc]

> -----Original Message-----
> From: 
> linuxppc-embedded-bounces+marc.howard=kla-tencor.com at ozlabs.or
> g 
> [mailto:linuxppc-embedded-bounces+marc.howard=kla-tencor.com at o
> zlabs.org] On Behalf Of Ed Goforth
> Sent: Tuesday, February 14, 2006 1:47 PM
> To: linuxppc-embedded at ozlabs.org
> Subject: Re: 440gx GPIO
> ..... 
> Well, I was able to manipulate GPIO9, GPIO10 and GPIO12.  It's time to
> turn it over to the hardware people.
> 

It's AMCC's fault.  They aren't listing the latest errata on their
website.  I downloaded their rev 3.1 ver 1.03 errata last August.
However if you look today you get the rev 3.1 ver 1.02 release.

In the 1.03 errata there is the following bug listed:

*************

GPIO_1:SDR0_PFC[G11E] has no effect.
Category: 6
Overview:
The SDR0_PFC[G11E] bit does not control GPIO11, thus meaning that GPIO11
is always active (unless EMAC group 4 is selected and both GPHYs are in
modes 0 or 1).
   
Impact:No impact.
Workaround:
None.

**************

Thus the PFC bit doesn't do anything.  If you're using group 4 "modes 0
or 1" (which mode field are they talking about here?) you're screwed,
you can't use GPIO11.

Curious how they think this has "No impact".  If you're running RGMII
you don't need that pin and it should be available for GPIO11 but
apparently it isn't.

Marc