Speed of plb_temac 3.00 on ML403

[Michael Galassi]

>My question is now: Has anybody deeper knowledge how ethernet and sgDMA
>works? How deep is the PPC involved in the data transfer? Or does the
>Temac-core handle the datatransfer to DDR-memory autonomous?

Thomas,

If you cut & pasted directly from my design you may be running without
DMA, which in turn implies running without checksum offload and DRE.
The plb_temac shrinks to about half it's size this way, but if you're
performance bound you probably want to turn DMA back on in your mhs
file:

 PARAMETER C_DMA_TYPE = 3
 PARAMETER C_INCLUDE_RX_CSUM = 1
 PARAMETER C_INCLUDE_TX_CSUM = 1
 PARAMETER C_RX_DRE_TYPE = 1
 PARAMETER C_TX_DRE_TYPE = 1
 PARAMETER C_RXFIFO_DEPTH = 32768

You'll have to regenerate the xparameters file too if you make these
changes (in xps: Software -> Generate Libraries and BSPs).

There may also be issues with the IP stack in the 2.4 linux kernels.
If you have the option, an experiment with at 2.6 stack would be
ammusing.

-michael