Some problem about code reading

Wang Haiying-r54964 Haiying.Wang at
Thu Aug 31 01:05:39 EST 2006

please read the following from MPC85xx UM about the sequence on how to
write CCSRBAR:
When the e500 core is writing to CCSRBAR, it should use the following

- Read the current value of CCSRBAR using a load word instruction
followed by an

    isync. This forces all accesses to configuration space to complete.

- Write the new value to CCSRBAR.

- Perform a load of an address that does not access configuration space
or the on-chip

SRAM, but has an address mapping already in effect (for example, boot

Follow this load with an isync.

- Read the contents of CCSRBAR from its new location, followed by
another isync



The codes  between line 287-294 complete the third step above.



	From: at
[ at]
On Behalf Of enorm
	Sent: Wednesday, August 30, 2006 9:46 AM
	To: linuxppc-embedded at
	Subject: Some problem about code reading 
	  I met some problems when reading sourcecode of u-boot 1.1.4
(for mpc85xx)
	file /cpu/mpc85xx/start.s line 276
	277.    /* Special sequence needed to update CCSRBAR itself */
	278.    lis r4, CFG_CCSRBAR_DEFAULT at h
	279.    ori r4, r4, CFG_CCSRBAR_DEFAULT at l
	281.    lis r5, CFG_CCSRBAR at h
	282.    ori r5, r5, CFG_CCSRBAR at l
	283.    srwi r6,r5,12
	284.    stw r6, 0(r4)
	285.    isync
	287.     lis r5, 0xffff
	288.     ori r5,r5,0xf000
	289.     lwz r5, 0(r5)
	290.     isync
	292.    lis r3, CFG_CCSRBAR at h
	293.    lwz r5, CFG_CCSRBAR at l(r3)
	294.     isync
	295.    #endif
	I think it means if we don't use default CCSRBAR, we put the
CCSRBAR addr actually used to the proper place in default CCSRBAR, so
that it can jump to the addr we want to automatically.(line 276-286).
	But, I don't know what line 287-294 does. Can some one tell me
	Thanks for your help. 

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