tah reset?

[Sanjay Bajaj]

FYI,

I did find the source of the reset tah issue. The physical address of TAH 0 and TAH 1 was ending in B00h and D00h respectively. But in the UM, it ends in B50 and D50. the file affected is ibm440gx.c in arch/ppc/platforms.

Thanks,
Sanjay

-----Original Message-----
From: Eugene Surovegin [mailto:ebs at ebshome.net]
Sent: Thursday, May 19, 2005 2:23 PM
To: Sanjay Bajaj
Cc: linuxppc-embedded at ozlabs.org
Subject: Re: tah reset?


On Thu, May 19, 2005 at 02:14:20PM -0400, Sanjay Bajaj wrote:
> While trying to reset the TAH on emac2 of PPC440GX, the Soft Reset 
> (SR) bit never resets itself to 0. Does anybody know the reason for 
> it?

Did you enable TAH0 in SDR0_MFR register?

Also, I don't remember for sure, but TAH may have the same problem as 
EMAC, namely, it won't go out of reset if there is no RX clock from 
PHY.

-- 
Eugene