[PATCH 1/3] SPI bus core infrastructure

[Eugene Surovegin]

On Sat, Jul 23, 2005 at 10:07:38AM -0400, Grant Likely wrote:
> Patch to add support for SPI busses.  SPI bus master drivers and SPI
> slave drivers register with the SPI infrastructure.
> 
> +#define SPI_CLKEDGE_RISING	0
> +#define SPI_CLKEDGE_FALLING	1
> +struct spi_bus_ops {
> +	int (*transfer) (struct spi_bus *bus, int id, int clkedge,
> +	                 uint8_t *in, const uint8_t *out, size_t count);
> +};

This isn't enough.

You must have a way to specify clock frequency, data order (which bit 
goes first, char length.

Take a look at how PowerQUICC defines SPI peripheral, to get an idea 
on what should be made configurable.

This is what I use on PowerQUICC as SPI interface:

/* SPI parameters for a specific client.
 * Most of them have the same meaning as in SPMODE register
 */
struct pq2_spi_client {
    unsigned int clock_invert : 1;
    unsigned int clock_phase : 1;
    unsigned int reverse_data : 1;

    int char_length;
    int clock;  /* in Hz */
    const char *name;

    void (*cs_control)(int assert);
};

int pq2_spi_xfer(struct pq2_spi_client*, const u8 *tx_buf, u8 *rx_buf, int len);