CPU15 errata workaround for 8xx by WD

Wrobel Heinz-r39252 Heinz.Wrobel at freescale.com
Wed Jan 5 04:07:20 EST 2005

Wolfgang, Joakim,
> I have to admit that I didn't believe our customer when  he  
> reported that  he has problems that were caused by the CPU15 
> bug - I never saw this on any other 8xx processor before, and 
> as you say  it  has  been mentioned  in  all errata sheets I 
> can remember. As far as I can tell it is only the MPC870/885 
> duet family of processors where this  CPU15 bug actually 
> hits. I have no idea why.

CPU15 is highly timing dependent. Even a single clock difference in the bus interface can make it (dis)appear.
It can happen on Duet's as on any other 8xx ... or not.

The simple workaround of invalidating the prev/next page is exactly that. Simple. It works, but for code with page locality it can hurt performance because you would get excessive reloads. A smarter workaround affecting only pages that need the workaround is preferrable, if it fits into the MMU table framework.


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