8xx bus monitoring

[Robin Gilks]

Pantelis Antoniou wrote:
>>>
>>> You get a machine check exception.
>>>
>>> It's pretty obvious then :)
>>>
>>
>> Using a 2.4.22 based kernel, as far as I can see a machine check 
>> should be trapped (its only allowed to cause a reset in the reboot 
>> code I think). Assuming I got it right and it really is trapped, how 
>> come I always get a reset:-((
>>
>> Any pointers to the code that does setup for causing an exception 
>> (rather than reset) would be appreciated.
>>
> 
> Check the MSR register at the time of the access.
> Is RI set? If not instead of an exception you get a reset...

I don't understand this - the whole point is that an exception occurs 
asynchronously and therefore I don't know where the access it, except of 
course I don't get an exception!!!

Where (insert name of source file in kernel tree) is RI set in MSR (or 
should be set but is missing from the kernel I'm using) so as to ensure 
that an exception occurs and how does the kernel distinguish a bus 
monitor timeout from other causes.

If the kernel (or the MPC8xx) is not capable of this then I guess I'll 
just have to fix the hardware :-((


-- 
Robin Gilks
Senior Design Engineer          Phone: (+64)(3) 357 1569
Tait Electronics                Fax  :  (+64)(3) 359 4632
PO Box 1645 Christchurch        Email : robin.gilks at tait.co.nz
New Zealand

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