Address mapping PPC 405

[Grant Likely]

On 8/28/05, Jon Masters <jonmasters at gmail.com> wrote:
> On 8/26/05, P. Sadik <psadik at gmail.com> wrote:
> 
> Lovely. We don't do it that way on 405 but we could - since the MMU is
> heavy soft assisted we could do that - we actually have everything run
> through the MMU once we've done initial MMU setup, but we do have the
> ability to mark ranges of addresses for IO and have the concept of TLB
> pinning to lock ranges of kernel addresses in large translated (BAT
> like for bigger PPC users) regions using just a few TLB slots. There
> is also a ZPR (zone protection register), but that's mostly used to
> fake the usual USER/KERNEL page distinction.
I believe TLB pinning was removed in 2.6 in favor of large TLB entries
for kernel space.  Matt Porter pointed this out to me about a week
ago.  This will not matter of course if you're not using 2.6.

Matt, is there any documentation covering the new design in the kernel tree?

Cheers,
g.