[26-devel] v2.6 performance slowdown on MPC8xx: Measuring TLB cache misses

Dan Malek dan at embeddededge.com
Sun Apr 24 08:09:11 EST 2005

On Apr 23, 2005, at 5:51 PM, Joakim Tjernlund wrote:

> Well, every instruction counts. I this case we would have saved
> 2 in ITLB Miss, 3 in DTLB Miss and a cache line write in both.

You have already read the PTE and instructions into the cache,
there are no branches, but not a big deal.

> Would be nice to do away with the kernel space test, but thats a lot 
> harder.

With some clever first level pointer page creation and management
we could do this, but it would be custom 8xx code in generic files.


	-- Dan

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